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| rej09b0392-0064 m16c/64 group hardware manual renesas mcu m16c family / m16c/60 series all information contained in these material s, including products and product specifi- cations, represents information on the produc t at the time of publication and is sub- ject to change by renesas technology corp. without notice. please review the latest information published by renesas technology corp. through various means, including the renesas technology co rp. website (http://www.renesas.com). rev.0.64 revision date: oct 12, 2007 16 www.renesas.com m16c/64 group hardware manual preliminary
1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes regarding these materials general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products. how to use this manual 1. purpose and target readers this manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the mcu. it is intended for users designing application systems incorporating the mcu. a basic knowledge of electric circuits, logical circuits , and mcus is necessary in order to use this manual. the manual comprises an overview of the product; descriptions of the cpu, system control functions, peripheral functions, and electrical characteristics; and usage notes. particular attention should be paid to the precautio nary notes when using the manual. these notes occur within the body of the text, at the end of each section, and in the usage notes section. the revision history summarizes the loca tions of revisions and additions. it does not list all revisions. refer to the text of the manual for details. the following documents apply to the m16c/64 group. make sure to refer to the latest versions of these documents. the newest versions of the documents listed may be obtained from the renesas technology web site. document type description document title document no. datasheet hardware overview and elec trical characteristics m16c/64 group datasheet rej03b0216 hardware manual hardware specific ations (pin assignments, mem- ory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description note: refer to the applic ation notes for details on using peripheral functions. m16c/64 group hardware manual this hardware manual application note information on using peripheral functions and application examples sample programs information on writing programs in assembly lan- guage and c available from renesas technol- ogy web site. renesas technical update product specifications, updates on documents, etc. 2. notation of numbers and symbols the notation conventions fo r register names, bit names, numbers, and symbols used in this manual are described below. (1) register names, bit names, and pin names registers, bits, and pins are referred to in the text by symbols. the symbol is accompanied by the word ?register,? ?bit,? or ?pin? to distinguish the three categories. examples the pm03 bit in the pm0 register p3_5 pin, vcc pin (2) notation of numbers the indication ?b? is appended to numeric values given in binary format. however, nothing is appended to the values of single bits. the indication ?h? is appended to numeric values given in hexadecimal format. nothing is appended to numeric values given in decimal format. examples binary: 11b hexadecimal: efa0h decimal: 1234 3. register notation the symbols and terms used in register diagrams are described below. *1 blank: set to 0 or 1 according to the application. 0: set to 0. 1: set to 1. x: nothing is assigned. *2 rw: read and write. ro: read only. wo: write only. ? : nothing is assigned. *3 ? reserved bit reserved bit. set to specified value. *4 ? nothing is assigned nothing is assigned to the bit. as the bit may be us ed for future functions, if necessary, set to 0. ? do not set to a value operation is not guaranteed when a value is set. ? function varies according to the operating mode. the function of the bit varies with the peripheral fu nction mode. refer to the re gister diagram for infor- mation on the individual modes. xxx register symbol address after reset xxx xxx 00h bit name bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 xxx bits 1 0: xxx 0 1: xxx 1 0: do not set. 1 1: xxx b1 b0 xxx1 xxx0 xxx4 reserved bits xxx5 xxx7 xxx6 function nothing is assigned. if necessary, set to 0. when read, the content is undefined. xxx bit function varies according to the operating mode. set to 0. 0 (b3) (b2) rw rw rw rw wo rw ro xxx bits 0: xxx 1: xxx *1 *2 *3 *4 4. list of abbreviat ions and acronyms abbreviation full form acia asynchronous communication interface adapter bps bits per second crc cyclic redundancy check dma direct memory access dmac direct memory access controller gsm global system for mobile communications hi-z high impedance iebus inter equipment bus i/o input/output irda infrared data association lsb least significant bit msb most significant bit nc non-connection pll phase locked loop pwm pulse width modulation sfr special function registers sim subscriber identity module uart universal asynchronous receiver/transmitter vco voltage controlled oscillator all trademarks and registered trademarks ar e the property of their respective owners. iebus is a registered trademark of nec electronics corporation. b - 1 address register symbol page 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 48 0005h processor mode register 1 pm1 49 0006h system clock control register 0 cm0 76 0007h system clock control register 1 cm1 77 0008h chip select control register csr 55 0009h 000ah protect register prcr 98 000bh data bank register dbr 67 000ch oscillation stop detection register cm2 78 000dh 000eh 000fh 0010h program 2 area control register prg2c 50 0011h 0012h peripheral clock select register pclkr 79 0013h 0014h 0015h clock prescaler reset flag cpsrf 141 0016h 0017h 0018h reset source determine flag rstfr 46 0019h voltage detection 2 circuit flag register vcr1 38 001ah voltage detection circuit operation enable register vcr2 38 001bh chip select expansion control register cse 62 001ch pll control register 0 plc0 80 001dh 001eh processor mode register 2 pm2 79 001fh low voltage detection interrupt register d4int 39 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002ah voltage monitor 0 circuit control register vw0c 40 002bh 002ch 002dh 002eh 002fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh 0040h 0041h address register symbol page 0042h int7 interrupt control register int7ic 106 0043h int6 interrupt control register int6ic 106 0044h int3 interrupt control register int3ic 106 0045h timer b5 interrupt control register tb5ic 105 0046h timer b4 interrupt control register, uart1 bus collision detection interrupt control register tb4ic, u1bcnic 105 0047h timer b3 interrupt control register, uart0 bus collision detection interrupt control register tb3ic, u0bcnic 105 0048h si/o4 interrupt control register, int5 inter- rupt control register s4ic, int5ic 106 0049h si/o3 interrupt control register, int4 inter- rupt control register s3ic, int4ic 106 004ah uart2 bus collision detection interrupt control register bcnic 106 004bh dma0 interrupt control register dm0ic 105 004ch dma1 interrupt control register dm1ic 105 004dh key input interrupt control register kupic 105 004eh a/d conversion interrupt control register adic 105 004fh uart2 transmit interrupt control register s2tic 105 0050h uart2 receive interrupt control register s2ric 105 0051h uart0 transmit interrupt control register s0tic 105 0052h uart0 receive interrupt control register s0ric 105 0053h uart1 transmit interrupt control register s1tic 105 0054h uart1 receive interrupt control register s1ric 105 0055h timer a0 interrupt control register ta0ic 105 0056h timer a1 interrupt control register ta1ic 105 0057h timer a2 interrupt control register ta2ic 105 0058h timer a3 interrupt control register ta3ic 105 0059h timer a4 interrupt control register ta4ic 105 005ah timer b0 interrupt control register tb0ic 105 005bh timer b1 interrupt control register tb1ic 105 005ch timer b2 interrupt control register tb2ic 105 005dh int0 interrupt control register int0ic 106 005eh int1 interrupt control register int1ic 106 005fh int2 interrupt control register int2ic 106 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h dma2 interrupt control register dm2ic 105 006ah dma3 interrupt control register dm3ic 105 006bh uart5 bus collision detection interrupt control register u5bcnic 105 006ch uart5 transmit interrupt control register s5tic 105 006dh uart5 receive interrupt control register s5ric 105 006eh uart6 bus collision detection interrupt control register u6bcnic 105 006fh uart6 transmit interrupt control register s6tic 105 0070h uart6 receive interrupt control register s6ric 105 0071h uart7 bus collision detection interrupt control register u7bcnic 105 0072h uart7 transmit interrupt control register s7tic 105 0073h uart7 receive interrupt control register s7ric 105 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh d080h to d17fh sfr page reference note: 1. blank columns are all re served space. no access is allowed. b - 2 address register symbol page 0180h dma0 source pointer sar0 128 0181h 0182h 0183h 0184h dma0 destination pointer dar0 128 0185h 0186h 0187h 0188h dma0 transfer counter tcr0 128 0189h 018ah 018bh 018ch dma0 control register dm0con 128 018dh 018eh 018fh 0190h dma1 source pointer sar1 128 0191h 0192h 0193h 0194h dma1 destination pointer dar1 128 0195h 0196h 0197h 0198h dma1 transfer counter tcr1 128 0199h 019ah 019bh 019ch dma1 control register dm1con 127 019dh 019eh 019fh 01a0h dma2 source pointer sar2 128 01a1h 01a2h 01a3h 01a4h dma2 destination pointer dar2 128 01a5h 01a6h 01a7h 01a8h dma2 transfer counter tcr2 128 01a9h 01aah 01abh 01ach dma2 control register dm2con 127 01adh 01aeh 01afh 01b0h dma3 source pointer sar3 128 01b1h 01b2h 01b3h 01b4h dma3 destination pointer dar3 128 01b5h 01b6h 01b7h 01b8h dma3 transfer counter tcr3 128 01b9h 01bah 01bbh 01bch dma3 control register dm3con 128 01bdh 01beh 01bfh 01c0h 01c1h 01c2h address register symbol page 01c3h 01c4h 01c5h 01c6h 01c7h 01c8h timer b count source select register 0 tbcs0 157 01c9h timer b count source select register 1 tbcs1 157 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h timer a count source select register 0 tacs0 141 01d1h timer a count source select register 1 tacs1 141 01d2h timer a count source select register 2 tacs2 142 01d3h 01d4h 01d5h timer a waveform output function select register tapofs 142 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01deh 01dch 01ddh 01dfh 01e0h 01e1h 01e2h 01e3h 01e4h 01e5h 01e6h 01e7h 01e8h timer b count source select register 2 tbcs2 157 01e9h timer b count source select register 3 tbcs3 157 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h 01f1h 01f2h 01f3h 01f4h 01f5h 01f6h 01f7h 01f8h 01f9h 01fah 01fbh 01fch 01fdh 01feh 01ffh 0200h 0201h 0202h 0203h 0204h note: 1. blank columns are all re served space. no access is allowed. b - 3 address register symbol page 0205h interrupt source select register 3 ifsr3a 114 0206h interrupt source select register 2 ifsr2a 114 0207h interrupt source select register ifsr 113 0208h 0209h 020ah 020bh 020ch 020dh 020eh address match interrupt enable register aier 117 020fh address match interrupt enable register 2 aier2 117 0210h address match interrupt register 0 rmad0 117 0211h 0212h 0213h 0214h address match interrupt register 1 rmad1 117 0215h 0216h 0217h 0218h address match interrupt register 2 rmad2 117 0219h 021ah 021bh 021ch address match interrupt register 3 rmad3 117 021dh 021eh 021fh 0220h flash memory control register 0 fmr0 272 0221h flash memory control register 1 fmr1 273 0222h flash memory control register 2 fmr2 274 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022ah 022bh 022ch 022dh 022eh 022fh 0230h flash memory control register 6 fmr6 275 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023ah 023bh 023ch 023dh 023eh 023fh 0240h 0241h 0242h 0243h 0244h uart0 special mode register 4 u0smr4 185 0245h uart0 special mode register 3 u0smr3 184 0246h uart0 special mode register 2 u0smr2 184 0247h uart0 special mode register u0smr 183 0248h uart0 transmit/receive mode register u0mr 180 address register symbol page 0249h uart0 bit rate register u0brg 180 024ah uart0 transmit buffer register u0tb 179 024bh 024ch uart0 transmit/receive control register 0 u0c0 181 024dh uart0 transmit/receive control register 1 u0c1 182 024eh uart0 receive buffer register u0rb 179 024fh 0250h uart transmit/receive control register 2 ucon 183 0251h 0252h 0253h 0254h uart1 special mode register 4 u1smr4 185 0255h uart1 special mode register 3 u1smr3 184 0256h uart1 special mode register 2 u1smr2 184 0257h uart1 special mode register u1smr 183 0258h uart1 transmit/receive mode register u1mr 180 0259h uart1 bit rate register u1brg 180 025ah uart1 transmit buffer register u1tb 170 025bh 025ch uart1 transmit/receive control register 0 u1c0 180 025dh uart1 transmit/receive control register 1 u1c1 182 025eh uart1 receive buffer register u1rb 170 025fh 0260h 0261h 0262h 0263h 0264h uart2 special mode register 4 u2smr4 185 0265h uart2 special mode register 3 u2smr3 184 0266h uart2 special mode register 2 u2smr2 184 0267h uart2 special mode register u2smr 183 0268h uart2 transmit/receive mode register u2mr 180 0269h uart2 bit rate register u2brg 180 026ah uart2 transmit buffer register u2tb 170 026bh 026ch uart2 transmit/receive control register 0 u2c0 181 026dh uart2 transmit/receive control register 1 u2c1 182 026eh uart2 receive buffer register u2rb 179 026fh 0270h si/o3 transmit/receive register s3trr 224 0271h 0272h si/o3 control register s3c 224 0273h si/o3 bit rate register s3brg 224 0274h si/o4 transmit/receive register s4trr 224 0275h 0276h si/o4 control register s4c 224 0277h si/o4 bit rate register s4brg 224 0278h si/o34 control register 2 s34c2 225 0279h 027ah 027bh 027ch 027dh 027eh 027fh 0280h 0281h 0282h 0283h 0284h uart5 special mode register 4 u5smr4 185 0285h uart5 special mode register 3 u5smr3 184 0286h uart5 special mode register 2 u5smr2 184 0287h uart5 special mode register u5smr 183 0288h uart5 transmit/receive mode register u5mr 180 0289h uart5 bit rate register u5brg 180 note: 1. blank columns are all reserved space. no access is allowed. b - 4 address register symbol page 028ah uart5 transmit buffer register u5tb 179 028bh 028ch uart5 transmit/receive control register 0 u5c0 181 028dh uart5 transmit/receive control register 1 u5c1 182 028eh uart5 receive buffer register u5rb 170 028fh 0290h 0291h 0292h 0293h 0294h uart6 special mode register 4 u6smr4 185 0295h uart6 special mode register 3 u6smr3 184 0296h uart6 special mode register 2 u6smr2 184 0297h uart6 special mode register u6smr 183 0298h uart6 transmit/receive mode register u6mr 180 0299h uart6 bit rate register u6brg 180 029ah uart6 transmit buffer register u6tb 179 029bh 029ch uart6 transmit/receive control register 0 u6c0 181 029dh uart6 transmit/receive control register 1 u6c1 182 029eh uart6 receive buffer register u6rb 179 029fh 02a0h 02a1h 02a2h 02a3h 02a4h uart7 special mode register 4 u7smr4 185 02a5h uart7 special mode register 3 u7smr3 184 02a6h uart7 special mode register 2 u7smr2 184 02a7h uart7 special mode register u7smr 183 02a8h uart7 transmit/receive mode register u7mr 180 02a9h uart7 bit rate register u7brg 180 02aah uart7 transmit buffer register u7tb 179 02abh 02ach uart7 transmit/receive control register 0 u7c0 181 02adh uart7 transmit/receive control register 1 u7c1 182 02aeh uart7 receive buffer register u7rb 179 02afh 02b0h to 02ffh 0300h timer b3,4,5 count start flag tbsr 156 0301h 0302h timer a1-1 register ta11 170 0303h 0304h timer a2-1 register ta21 170 0305h 0306h timer a4-1 register ta41 170 0307h 0308h three-phase pwm control register 0 invc0 167 0309h three-phase pwm control register 1 invc1 168 030ah three-phase output buffer register 0 idb0 169 030bh three-phase output buffer register 1 idb1 169 030ch dead time timer dtt 169 030dh timer b2 interrupt generation frequency set counter ictb2 169 030eh 030fh 0310h timer b3 register tb3 155 0311h 0312h timer b4 register tb4 155 0313h 0314h timer b5 register tb5 155 0315h 0316h 0317h 0318h 0319h address register symbol page 031ah 031bh timer b3 mode register tb3mr 155 031ch timer b4 mode register tb4mr 155 031dh timer b5 mode register tb5mr 155 031eh 031fh 0320h count start flag tabsr 156 0321h 0322h one-shot start flag onsf 140 0323h trigger select register trgsr 140 0324h up/down flag udf 139 0325h 0326h timer a0 register ta0 152 0327h 0328h timer a1 register ta1 152 0329h 032ah timer a2 register ta2 152 032bh 032ch timer a3 register ta3 152 032dh 032eh timer a4 register ta4 152 032fh 0330h timer b0 register tb0 155 0331h 0332h timer b1 register tb1 155 0333h 0334h timer b2 register tb2 155 0335h 0336h timer a0 mode register ta0mr 138 0337h timer a1 mode register ta1mr 138 0338h timer a2 mode register ta2mr 138 0339h timer a3 mode register ta3mr 138 033ah timer a4 mode register ta4mr 138 033bh timer b0 mode register tb0mr 155 033ch timer b1 mode register tb1mr 155 033dh timer b2 mode register tb2mr 155 033eh timer b2 special mode register tb2sc 170 033fh 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034ah 034bh 034ch 034dh 034eh 034fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035ah 035bh note: 1. blank columns are all re served space. no access is allowed. b - 5 address register symbol page 035ch 035dh 035eh 035fh 0360h pull-up control register 0 pur0 258 0361h pull-up control register 1 pur1 258 0362h pull-up control register 2 pur2 259 0363h 0364h 0365h 0366h port control register pcr 259 0367h 0368h 0369h 036ah 036bh 036ch 036dh 036eh 036fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037ah 037bh 037ch count source protection mode register cspr 120 037dh watchdog timer reset register wdtr 119 037eh watchdog timer start register wdts 119 037fh watchdog timer control register wdc 119 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038ah 038bh 038ch 038dh 038eh 038fh 0390h dma2 source select register dm2sl 125 0391h 0392h dma3 source select register dm3sl 125 0393h 0394h 0395h 0396h 0397h 0398h dma0 source select register dm0sl 125 0399h 039ah dma1 source select register dm1sl 125 039bh 039ch 039dh 039eh 039fh address register symbol page 03a0h 03a1h 03a2h 03a3h 03a4h 03a5h 03a6h 03a7h 03a8h 03a9h 03aah 03abh 03ach 03adh 03aeh 03afh 03b0h 03b1h 03b2h 03b3h 03b4h 03b5h 03b6h 03b7h 03b8h 03b9h 03bah 03bbh 03bch crc data register crcd 248 03bdh 03beh crc input register crcin 248 03bfh 03c0h a/d register 0 ad0 233 03c1h 03c2h a/d register 1 ad1 233 03c3h 03c4h a/d register 2 ad2 233 03c5h 03c6h a/d register 3 ad3 233 03c7h 03c8h a/d register 4 ad4 233 03c9h 03cah a/d register 5 ad5 233 03cbh 03cch a/d register 6 ad6 233 03cdh 03ceh a/d register 7 ad7 233 03cfh 03d0h 03d1h 03d2h 03d3h 03d4h a/d control register 2 adcon2 233 03d5h 03d6h a/d control register 0 adcon0 232 03d7h a/d control register 1 adcon1 232 03d8h d/a0 register da0 247 03d9h 03dah d/a1 register da1 247 03dbh 03dch d/a control register dacon 247 03ddh 03deh 03dfh 03e0h port p0 register p0 257 03e1h port p1 register p1 257 03e2h port p0 direction register pd0 256 03e3h port p1 direction register pd1 256 note: 1. blank columns are all re served space. no access is allowed. b - 6 address register symbol page 03e4h port p2 register p2 257 03e5h port p3 register p3 257 03e6h port p2 direction register pd2 256 03e7h port p3 direction register pd3 256 03e8h port p4 register p4 257 03e9h port p5 register p5 257 03eah port p4 direction register pd4 256 03ebh port p5 direction register pd5 256 03ech port p6 register p6 257 03edh port p7 register p7 257 03eeh port p6 direction register pd6 256 03efh port p7 direction register pd7 256 03f0h port p8 register p8 257 03f1h port p9 register p9 257 03f2h port p8 direction register pd8 256 03f3h port p9 direction register pd9 256 03f4h port p10 register p10 257 03f5h 03f6h port p10 direction register pd10 256 03f7h 03f8h 03f9h 03fah 03fbh 03fch 03fdh 03feh 03ffh d000h to d7ffh ofs1 optional feature select address ofs1 269 note: 1. blank columns are all reserved space. no access is allowed. 1- 1 table of contents sfr page reference .......... ................ ................ ................. ................ ................. ...........b-1 1. overview ............. .............................. .............................. ......................... 1 1.1 features ........... ................. .............. .............. .............. .............. .............. ............ 1 1.1.1 applications ........... ................ ................. .............. .............. .............. ............ 1 1.2 specifications ............. ................ ................ ................. .............. .............. ............ 2 1.3 product list ............... ................ ................ ................. .............. .............. ............ 4 1.4 block diagram .............. ................ ................. .............. .............. .............. ............ 6 1.5 pin assignments.................. ................ ................. ................ ................. .............. 7 1.6 pin functions.............. ................ ................ ................. .............. .............. .......... 11 2. central processing unit (c pu)............................ ................................... 14 2.1 data registers (r0, r1, r2 and r3).................... ................ ................. ............ 14 2.2 address registers (a0 a nd a1).............. ................ ................. ................ .......... 15 2.3 frame base registers (fb)... ................. ................ ................. ................ .......... 15 2.4 interrupt table regist er (intb) ........... ................. ................ ................. ............ 15 2.5 program counter (pc) .......... ................. ................ ................. ................ .......... 15 2.6 user stack pointer (usp) and interrupt sta ck pointer (isp) .......... ........... ........ 15 2.7 static base register (sb)............. ................. .............. .............. .............. .......... 15 2.8 flag register (flg).... ................ ................ ................. .............. .............. .......... 15 2.8.1 carry flag (c flag)............ ................ ................ ................. .............. .......... 15 2.8.2 debug flag (d flag) ............ ................ ................. .............. .............. .......... 15 2.8.3 zero flag (z flag).. ................ ................. .............. .............. .............. .......... 15 2.8.4 sign flag (s flag). ................. ................. .............. .............. .............. .......... 15 2.8.5 register bank select flag (b flag) ............... ................ ................. ............ 15 2.8.6 overflow flag (o flag) ........ ................ ................. .............. .............. .......... 15 2.8.7 interrupt enable flag (i flag).................. .............. .............. .............. .......... 15 2.8.8 stack pointer select flag (u flag) .................. ................. ................ .......... 16 2.8.9 processor interrupt priority level (ipl) ... ................. ............... ........... ........ 16 2.8.10 reserved space ............. ................. ................ ................. ................ .......... 16 1- 2 3. memory ..................... .............................. .............................. ................. 17 4. special function re gisters (sfrs) ......... .............................. ................. 18 5. reset ......................... .............................. .............................. ................. 32 5.1 hardware reset 1 ........ ................ ................. .............. .............. .............. .......... 32 5.1.1 reset on a stable s upply voltage .............. .............. ............... ........... ........ 32 5.1.2 power-on reset....... ................. .............. .............. .............. .............. .......... 32 5.2 brown-out reset.................. ................ ................. ................ ................. ............ 35 5.3 software reset........... ................ ................ ................. .............. .............. .......... 35 5.4 watchdog timer reset............. ................ ................ ................. .............. .......... 35 5.5 oscillation stop detection reset . ............... ................. .............. .............. .......... 35 5.6 internal space ............ ................ ................ ................. .............. .............. .......... 36 6. voltage detection circuit . .............................. ........................ ................. 37 6.1 brown-out reset.................. ................ ................. ................ ................. ............ 41 6.2 low voltage detection interrupt ............. ................ ................. ................ .......... 42 6.3 limitations on exiting stop mo de ............. ................ ................. .............. .......... 44 6.4 limitations on exiting wait mode ........... ................ ................. ................ .......... 44 6.5 cold start-up / warm start- up discrimination.................. ............... ........... ........ 45 7. processor mode ................................ .............................. ....................... 47 7.1 types of processor mode...... ................. ................ ................. ................ .......... 47 7.2 setting processor modes ................ .............. .............. .............. .............. .......... 47 7.3 internal memory ......... ................ ................ ................. .............. .............. .......... 51 8. bus ............................ .............................. .............................. ................. 53 8.1 bus mode ............ ................ ................ ................. ................ ................. ............ 53 8.1.1 separate bus.................. ................. ................ ................. ................ .......... 53 8.1.2 multiplexed bus ....... ................. .............. .............. .............. .............. .......... 53 8.2 bus control.............. ................. ................ ................ ................. .............. .......... 54 8.2.1 address bus ............ ................. .............. .............. .............. .............. .......... 54 8.2.2 data bus.............. ................ ................ ................. .............. .............. .......... 54 8.2.3 chip select signal ............. ................ ................ ................. .............. .......... 54 8.2.4 read and write signals............ .............. .............. .............. .............. .......... 57 8.2.5 ale signal........... ................ ................ ................. .............. .............. .......... 57 8.2.6 rdy signal ................. .............. .............. .............. .............. .............. .......... 58 1- 3 8.2.7 hold signal................... ................. ................ ................. ................ .......... 59 8.2.8 bclk output ........... ................. .............. .............. .............. .............. .......... 59 8.2.9 external bus status when internal area is accessed .. ................. ............ 61 8.2.10 software wait ...... ................ ................ ................. .............. .............. .......... 61 9. memory space expansion f unction.................... ................................... 66 9.2 4-mbyte mode .............. ................ ................. .............. .............. .............. .......... 66 9.2.1 addresses 04000h to 3ffff h, c0000h to fffffh ........... .............. .......... 66 9.2.2 addresses 40000h to bffffh .. ................. .............. ............... ........... ........ 66 10. clock generation circuit . .............................. ........................ ................. 74 10.1 type of the clock gener ation circuit............. .............. .............. .............. .......... 74 10.1.1 main clock............. ................ ................. .............. .............. .............. .......... 81 10.1.2 sub clock .............. ................ ................. .............. .............. .............. .......... 82 10.1.3 125 khz on-chip o scillator clock (foco-s)............ ............... ........... ........ 83 10.1.4 pll clock .............. ................ ................. .............. .............. .............. .......... 83 10.2 cpu clock and peripher al function clock........ .............. ............... ........... ........ 86 10.2.1 cpu clock and bclk.......... ................ ................. .............. .............. .......... 86 10.2.2 peripheral function clock (f 1, fc32) ............... ................. ................ .......... 87 10.3 clock output function........... ................. ................ ................. ................ .......... 87 10.4 power control............. ................ ................ ................. .............. .............. .......... 88 10.4.1 normal operating m ode .................. ................ ................. ................ .......... 88 10.4.2 wait mode ............. ................ ................. .............. .............. .............. .......... 90 10.4.3 stop mode ............. ................ ................. .............. .............. .............. .......... 92 10.5 system clock protection functi on ................ .............. .............. .............. .......... 95 10.6 oscillation stop and re-oscillation detect f unction ............ ................. ............ 96 10.6.1 operation when cm27 bit = 0 (oscillation stop detection reset) ............. 96 10.6.2 operation when cm27 bi t = 1 (oscillation stop and re-oscillation detect interrupt) ................. .............. .............. .............. ........ 96 10.6.3 how to use oscillati on stop and re-oscillation detect function............... 97 11. protection ............ .............................. .............................. ....................... 98 12. interrupt ............... .............................. .............................. ....................... 99 12.1 type of interrupts ................ ................ ................. ................ ................. ............ 99 12.2 software interrupts ..... ................ ................ .............. ............... .............. .......... 100 12.2.1 undefined instruction interrup t ................. .............. .............. ............ ........ 100 1- 4 12.2.2 overflow interrupt .............. ................ ................ ............... .............. .......... 100 12.2.4 int instruction interrupt..... ................ ................ ............... .............. .......... 100 12.3 hardware interrupts............... ................. ................ ................. .............. .......... 101 12.3.1 special interrupts............ ................. ................ ................. .............. .......... 101 12.3.2 peripheral function interrupts ................ .............. .............. .............. ........ 101 12.4 interrupts and interrupt vector ................ ................ ................. .............. .......... 102 12.4.1 fixed vector tables ........... ................ ................ ............... .............. .......... 102 12.4.2 relocatable vector tables .. ................. .............. ............... .............. .......... 103 12.5 interrupt control ................ ................ ................ ................. ................ ............. 105 12.5.1 i flag................. ................. ................ ................ ............... .............. .......... 107 12.5.2 ir bit................. ................. ................ ................ ............... .............. .......... 107 12.5.3 bits ilvl2 to ilvl0 and ipl . ................ .............. ............... .............. .......... 107 12.5.4 interrupt sequence ............ ................ ................ ............... .............. .......... 108 12.5.5 interrupt response time ..... ................ .............. ............... .............. .......... 109 12.5.6 variation of ipl when in terrupt request is accepted .. ............... ............. 109 12.5.7 saving registers ..... .............. .............. .............. ............... .............. .......... 110 12.5.8 returning from an in terrupt routine ......... .............. .............. .............. .......111 12.5.9 interrupt priority .............. ................. ................ ................. ................ .........111 12.5.10 interrupt priority level se lect circuit .......... .............. ............... ........... .......111 12.6 int interrupt ................. ................ .............. .............. ............... .............. .......... 113 12.7 nmi interrupt ........... ................. ................ ................ ............... .............. .......... 115 12.8 key input interrupt............... ................ ................. ................ ................. .......... 115 12.9 address match interrupt ........... ................ ................ ............... .............. .......... 116 13. watchdog timer .................... .............................. ................................. 118 13.1 count source protecti on mode disabled ........ .............. .............. ............ ........ 121 13.2 count source protecti on mode enabled ......... .............. .............. ............ ........ 122 14. dmac........................ .............................. .............................. ............... 123 14.1 transfer cycles .......... ................ ................ .............. ............... .............. .......... 129 14.1.1 effect of source and destination addre sses ............... ................ ............. 129 14.1.2 effect of byte pin level ..... ................ .............. ............... .............. .......... 129 14.1.3 effect of software wait ... ................. ................ ................. .............. .......... 129 14.1.4 effect of rdy signal................. .............. .............. .............. .............. ........ 129 14.2 dma transfer cycles .......... ................ ................. ................ ................. .......... 131 14.3 dma enabled ............. ................ ................ .............. ............... .............. .......... 132 1- 5 14.4 dma request ............... ................ .............. .............. ............... .............. .......... 132 14.5 channel priority and dma transfer timing....... ................. ................ ............. 133 15. timers................. .............................. .............................. ..................... 134 15.1 timer a .................. ................ ................. ................ ................. .............. .......... 137 15.1.1 timer mode ........... ................ .............. .............. ............... .............. .......... 143 15.1.2 event counter mode.......... ................ ................ ............... .............. .......... 144 15.1.3 one-shot timer mode ......... ................ .............. ............... .............. .......... 149 15.1.4 pulse width modulation (pwm) mode...... .............. .............. ............ ........ 151 15.2 timer b .................. ................ ................. ................ ................. .............. .......... 154 15.2.1 timer mode ........... ................ .............. .............. ............... .............. .......... 158 15.2.2 event counter mode.......... ................ ................ ............... .............. .......... 160 15.2.3 pulse period and pulse width measur ement modes ........... ............ ........ 162 16. three-phase motor control time r function ........ ................................. 165 17. serial interface ................ .............................. ........................ ............... 175 17.1 uarti (i = 0 to 2, 5 to 7). .............. .............. .............. ............... .............. .......... 175 17.1.1 clock synchronous serial i/ o mode........... ................. ................ ............. 186 17.1.2 clock asynchronous serial i/o (uart) mo de............. ................ ............. 194 17.1.3 special mode 1 (i 2 c mode) .................... .............. .............. .............. ........ 202 17.1.4 special mode 2 ........ .............. .............. .............. ............... .............. .......... 212 17.1.5 special mode 3 (ie mode) .... ............... .............. ............... .............. .......... 216 17.1.6 special mode 4 (sim mode) (uart2) ...... .............. .............. ............ ........ 218 17.2 si/o3 and si/o4 .................. ................ ................. ................ ................. .......... 223 17.2.1 si/oi operati on timing .................... ................ ................. .............. .......... 227 17.2.2 clk polarity selection.... ................. ................ ................. .............. .......... 227 17.2.3 functions for setting an so uti initial value............. ............ ............ ........ 228 17.2.4 functions for selecting souti state after transmission...... ............ ........ 229 18. a/d converter........................ .................................... ........................... 230 18.1 mode description ........... .............. .............. .............. ............... .............. .......... 234 18.1.1 one-shot mode ................. ................ ................ ............... .............. .......... 234 18.1.2 repeat mode ........... .............. .............. .............. ............... .............. .......... 236 18.1.3 single sweep mode............. ................ .............. ............... .............. .......... 238 18.1.4 repeat sweep mode 0 ............. .............. .............. .............. .............. ........ 240 18.1.5 repeat sweep mode 1 ............. .............. .............. .............. .............. ........ 242 1- 6 18.2 conversion rate........... ................ .............. .............. ............... .............. .......... 244 18.3 extended analog input pins ..... ................ ................ ............... .............. .......... 244 18.4 current consumption reduci ng function ............ ................ ................. .......... 244 18.5 output impedance of sensor under a/d conversion ......... ................ ............. 245 19. d/a converter........................ .................................... ........................... 246 19.1 summary ................. ................. ................ ................ ............... .............. .......... 246 20. crc operation...................... .................................... ........................... 248 21. programmable i/o ports.. .............................. ........................ ............... 250 21.1 port pi direction register (pdi register, i = 0 to 10)..... .............. ............ ........ 250 21.2 port pi register (pi register , i = 0 to 10) ........ .............. .............. ............ ........ 250 21.3 pull-up control register 0 to pull -up control regist er 2 (registers pur0 to pur2) ............ ................ .............. .............. ............... .............. .......... 250 21.4 port control register (pcr register) ............... ................. ................ ............. 250 22. flash memory version..... .............................. ........................ ............... 263 22.1 memory map .............. ................ ................ .............. ............... .............. .......... 264 22.1.1 boot mode ............. ................ .............. .............. ............... .............. .......... 265 22.1.2 user boot function............ ................ ................ ............... .............. .......... 265 22.2 functions to prevent flash memory from rewriting ....... ............ ............ ........ 267 22.2.1 rom code protect function . .............. .............. ............... .............. .......... 267 22.2.2 id code check function ..... ................ .............. ............... .............. .......... 267 22.2.3 forced erase function ...... ................ ................ ............... .............. .......... 268 22.2.4 standard serial i/o mode di sable function ...... ............... .............. .......... 268 22.3 cpu rewrite mode....... ................ .............. .............. ............... .............. .......... 270 22.3.1 ew0 mode............. ................ .............. .............. ............... .............. .......... 271 22.3.2 ew1 mode............. ................ .............. .............. ............... .............. .......... 271 22.3.3 flash memory control register (registers fmr0, fmr1, fmr2 and fmr6).................. ................ ................ .............. ............... .............. .......... 271 22.3.4 precautions on cpu rewrit e mode............... ................ ................. .......... 282 22.3.5 software commands ........... ................ .............. ............... .............. .......... 284 22.3.6 data protect function........ ................ ................ ............... .............. .......... 290 22.3.7 status register ...... ................ .............. .............. ............... .............. .......... 290 22.3.8 full status check............ ................. ................ ................. .............. .......... 292 22.4 standard serial i/o mode ......... ................ ................ ............... .............. .......... 294 1- 7 22.4.1 id code check function ..... ................ .............. ............... .............. .......... 294 22.4.2 example of circuit application in t he standard serial i/o mode............... 298 22.5 parallel i/o mode..... ................. ................ ................ ............... .............. .......... 300 22.5.1 rom code protect function . .............. .............. ............... .............. .......... 300 23. electrical characteristic s ..................................... ................................. 301 23.1 electrical characteristics ..... ................ ................. ................ ................. .......... 301 24. precautions ......... .............................. .............................. ..................... 341 24.1 sfr .............. ................ ................ .............. .............. ............... .............. .......... 341 24.1.1 register setti ngs ................... .............. .............. ............... .............. .......... 341 24.2 reset ................ ................. ................ ................ ................. ................ ............. 342 24.2.1 vcc1 .............. ................ ................. ................ ................. .............. .......... 342 24.2.2 cnvss ........... ................ ................. ................ ................. .............. .......... 342 24.3 bus ................. ................ .............. .............. .............. ............... .............. .......... 343 24.4 pll frequency synthesizer ....... ................ .............. ............... .............. .......... 344 24.5 power control.......... ................. ................ ................ ............... .............. .......... 345 24.6 protect .............. ................. ................ ................ ................. ................ ............. 347 24.7 interrupt ................. ................ ................. ................ ................. .............. .......... 348 24.7.1 reading address 00000h . ................... .............. ............... .............. .......... 348 24.7.2 sp setting............ ................ ................ .............. ............... .............. .......... 348 24.7.3 nmi interrupt............... ................ ................ ................. ................ ............. 348 24.7.4 changing an interrupt generat e factor............. ............... .............. .......... 349 24.7.5 int interrupt ............... ................ ................ ................. ................ ............. 349 24.7.6 rewriting the interr upt control register ............... .............. .............. ........ 350 24.7.7 watchdog timer interrupt .... ................ .............. ............... .............. .......... 351 24.8 dmac.................. ................ ................ ................. ................ ................. .......... 352 24.8.1 write to the dmae bit in the dmicon regist er (i = 0 to 3).. ............ ........ 352 24.9 timers .............. ................. ................ ................ ................. ................ ............. 353 24.9.1 timer a ............. ................. ................ ................ ............... .............. .......... 353 24.9.2 timer b ............. ................. ................ ................ ............... .............. .......... 357 24.10 serial interface ........ ................. ................ ................ ............... .............. .......... 360 24.10.1 clock synchronous serial i/o .............. .............. ............... .............. .......... 360 24.10.2 uart (clock asynchronous serial i/o) mode............. ................ ............. 362 24.10.3 special mode 1 (i2c mode) .. ............... .............. ............... .............. .......... 362 24.10.4 special mode 4 (sim mode) .. .............. .............. ............... .............. .......... 362 1- 8 24.10.5 si/o3, si/o4 .......... ................ .............. .............. ............... .............. .......... 363 24.11 a/d converter.......... ................. ................ ................ ............... .............. .......... 364 24.12 programmable i/o ports........ ................. ................ ................. .............. .......... 366 24.13 flash memory version......... ................ ................. ................ ................. .......... 367 24.13.1 functions to inhibit rewr iting flash memory............ ............ ............ ........ 367 24.13.2 stop mode ............. ................ .............. .............. ............... .............. .......... 367 24.13.3 wait mode ............. ................ .............. .............. ............... .............. .......... 367 24.13.4 low power consumption mode, on-chip oscillator low po wer consumption mode ...... ................. .......... 367 24.13.5 writing command and data ..... .............. .............. .............. .............. ........ 367 24.13.6 program command ............. ................ .............. ............... .............. .......... 367 24.13.7 lock bit program command . .............. .............. ............... .............. .......... 367 24.13.8 operation speed................ ................ ................ ............... .............. .......... 368 24.13.9 instructions inhibited again st use........... .............. .............. .............. ........ 368 24.13.10 interrupts ............. ................ ................ .............. ............... .............. .......... 368 24.13.11 how to access....... ................ .............. .............. ............... .............. .......... 368 24.13.12 writing in the user rom area ............. .............. ............... .............. .......... 368 24.13.13 dma transfer .................. ................. ................ ................. .............. .......... 368 24.13.14 programming / erasing e ndurance and execution time ................ .......... 369 24.14 noise .............. ................ .............. .............. .............. ............... .............. .......... 370 appendix 1.package dimensions . .................................... ........................... 371 register inde x appendix 1-372 rej09b0392-0064 rev.0.64 oct 12, 2007 page 1 of 373 m16c/64 group renesas mcu preliminary 1. overview 1.1 features the m16c/64 group mcus incorporate the m16c/60 series cpu core and flash memory, employing sophisticated instructions for a high level of efficiency. with 1 mbyte of address space (expandable to 4 mbyte), this mcu is capable of execut ing instructions at high speed. in addiditon, the cpu core boasts a multiplier for high-speed operation processing. power consumption is low, and the m16c/64 group supp orts operating modes that allow additional power control. the mcu also uses an anti-noise configurat ion to reduce emissions of electromagnetic noise and is designed to withstand emi. integration of many pe ripheral functions, including multifunction timer and serial interface, reduces the number of system components. 1.1.1 applications audio, cameras, television, home appliance, office equipment, communication equipment, portable equipment, industrial equipment, etc. rej09b0392-0064 rev.0.64 oct 12, 2007 page 2 of 373 m16c/64 group 1. overview under development preliminary specification specification in this preliminary version is subject to change. 1.2 specifications tables 1.1 and 1.2 list spec ifications outline. note: 1. iebus is a registered trademark of nec electronics corporation. table 1.1 specifications (1) item function specification cpu central processing unit m16c/60 co re (multiplier: 16-bit 16-bit ! 32 bits, multiply and accumulate instruction: 16 16 + 32 ! 32 bits) ? number of basic instructions: 91 ? minimum instruction execution time: 40.0 ns ( f(bclk) = 25 mhz, vcc1 = vcc2 = 2.7 to 5.5 v) ? operating modes: single-chip, memory expansion, and microproces- sor memory rom, ram, data flash see table 1.3 product list . voltage detection voltage detection circuit low-voltage detection unit clock clock generation circuit ? 4 circuits: main clock, sub clock, on-chip oscillator (125 khz), pll ? oscillation stop detection: main clock oscillation stop detection and re- oscillation detection function ? frequency divider circuit: divide ratio selectable from 1, 2, 4, 8 and 16 ? low-power consumption modes: wait mode, stop mode external bus expansion bus and memory expansion ? address space: 1 mbyte ? external bus interface: 0 to 3 waits states, chip select 4 outputs, mem- ory area expansion function (up to 4 mbytes), 3 v, 5 v interface ? bus format: separate bus or multiplexed bus selectable, data bus width selectable (8 or 16 bits), number of address buses selectable (12, 16, or 20 buses) i/o ports programmable i/o ports ? cmos i/o ports: 85, selectable pull-up resistor ? nch open drain ports: 3 interrupts ? interrupt vectors: 70 ? external interrupt input: 13 ( nmi , int 8, key input 4) ? interrupt priority levels: 7 watchdog timer 15 bits 1 (with prescaler) automatic reset start function selectable dma dmac ? 4 channels, cycle steal mode ? trigger sources: 43 ? transfer modes: 2 (single transfer, repeat transfer) timer timer a 16-bit timer 5 timer mode, event counter mode, one shot timer mode, pulse width modulation (pwm) mode event counter two-phase pulse signal processing (two-phase encoder input) 3 channels timer b 16-bit timer 6 timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode timer functions for three- phase motor control three-phase inverter control (timer a1, timer a2, time r a4, timer b2), on-chip dead time timer serial inter- face uart0 to uart2, uart5 to uart7 clock synchronous/asynchronous 6 channels i 2 c-bus, iebus (1) , special mode 2, sim (uart2) si/o3, si/o4 clock synchronization only 2 channels rej09b0392-0064 rev.0.64 oct 12, 2007 page 3 of 373 m16c/64 group 1. overview under development preliminary specification specification in this preliminary version is subject to change. table 1.2 specifications (2) item function specification a/d converter 10-bit resolution 26 channels, including sample and hold function, conversion time: 1.72 s d/a converter 8-bit resolution 2 crc calculation circuit crc-ccitt (x 16 + x 12 + x 5 + 1) compliant flash memory programming and erasure power supply voltage: 2.7 v to 5.5 v programming and erasure endurance: 100 times program security: rom code protect, id code check debug function functions on-chip debug, on-board flash rewrite function, address match 4 operation frequency/supply voltage 25 mhz/vcc1 = vcc2 = 2.7 to 5.5 v power consumption 20 ma (25 mhz/vcc1 = vcc2 = 3 v) 3.0 a(vcc1 = vcc2 = 3 v, in stop mode) operating temperature -20c to 85c, -40c to 85c package 100-pin qfp: prqp0100jd-b (previous package code: 100p6f-a) 100-pin lqfp: plqp0100kb-a (pre vious package code: 100p6q-a) rej09b0392-0064 rev.0.64 oct 12, 2007 page 4 of 373 m16c/64 group 1. overview under development preliminary specification specification in this preliminary version is subject to change. 1.3 product list table 1.3 lists product information. figure 1.1 shows part numbers, memory sizes, and packages. (d) : under development note: 1. previous package codes are as follows. prqp0100jd-b: 100p6f-a, plqp0100kb-a: 100p6q-a figure 1.1 correspondence of part no., with memory size and package table 1.3 product list part no. rom capacity ram capacity package code remarks program rom 1 program rom 2 data flash r5f36406nfa (d) 128 kbytes 16 kbytes 4 kbytes 2 blocks 12 kbytes prqp0100jd-b operating temperature -20 c to 85 c r5f36406nfb (d) plqp0100kb-a r5f3640dnfa (d) 256 kbytes 16 kbytes 4 kbytes 2 blocks 16 kbytes prqp0100jd-b r5f3640dnfb (d) plqp0100kb-a r5f3640mnfa (d) 512 kbytes 16 kbytes 4 kbytes 2 blocks 31 kbytes prqp0100jd-b r5f3640mnfb (d) plqp0100kb-a r5f36406dfa (d) 128 kbytes 16 kbytes 4 kbytes 2 blocks 12 kbytes prqp0100jd-b operating temperature -40 c to 85 c r5f36406dfb (d) plqp0100kb-a r5f3640ddfa (d) 256 kbytes 16 kbytes 4 kbytes 2 blocks 16 kbytes prqp0100jd-b r5f3640ddfb (d) plqp0100kb-a r5f3640mdfa (d) 512 kbytes 16 kbytes 4 kbytes 2 blocks 31 kbytes prqp0100jd-b r5f3640mdfb (d) plqp0100kb-a package type: fa: package prqp0100jd-b (100p6f-a) fb: package plqp0100kb-a (100p6q-a) property code n: operating temperature -20 c to 85 c d: operating temperature -40 c to 85 c memory type: f: flash memory r 5 f 3 640 6 d fa renesas microcomputer renesas semiconductor m16c / 64 group memory capacity program rom 1 / ram 6: 128 kbytes / 12 kbytes d: 256 kbytes / 16 kbytes m: 512 kbytes / 31 kbytes 16-bit microcomputer part no. rej09b0392-0064 rev.0.64 oct 12, 2007 page 5 of 373 m16c/64 group 1. overview under development preliminary specification specification in this preliminary version is subject to change. figure 1.2 marking diagram of flash memory version (top view) m1 6 c r5f36406dfa xxxxxxx part no. (see figure 1.1 correspondence of part no., with memory size and package ) date code seven digits rej09b0392-0064 rev.0.64 oct 12, 2007 page 6 of 373 m16c/64 group 1. overview under development preliminary specification specification in this preliminary version is subject to change. 1.4 block diagram figure 1.3 is a m16c/64 group block diagram. figure 1.3 block diagram clock synchronous serial i/o (8 bits 2 channels) dmac (4 channels) internal peripheral functions clock generation circuits xin-xout xcin-xcout pll frequency synthesizer on-chip oscillator (125 khz) notes : 1. rom size depends on mcu type. 2. ram size depends on mcu type. port p0 8 port p1 8 port p2 8 8 8 8 port p5 port p4 port p3 uart or clock synchronous serial i/o (6 channels) vcc2 ports r0l r0h r1h r1l r2 r3 a0 a1 fb sb isp usp intb flg m16c/60 series cpu core memory rom (1) ram (2) multiplier pc watchdog timer (15 bits) a/d converter (10 bits 26 channels) crc calculation circuit (ccitt) (polynomial x 16 + x 12 + x 5 + 1) d/a converter (8 bits 2 channels) three-phase motor control circuit 8 8 8 port p7 port p8 port p9 port p10 8 port p6 8 timer (16-bit) outputs (timer a): 5 inputs (timer b): 6 vcc1 ports rej09b0392-0064 rev.0.64 oct 12, 2007 page 7 of 373 m16c/64 group 1. overview under development preliminary specification specification in this preliminary version is subject to change. 1.5 pin assignments figures 1.4 and 1.5 show pin assignments (top view). figure 1.4 pin assignment (top view) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 vref avss vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p7_4/ta2out/w avcc p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_3/da0/tb3in p9_4/da1/tb4in p9_5/anex0/clk4 p9_6/anex1/sout4 p9_1/tb1in/sin3 p9_2/tb2in/sout3 p7_2/clk2/ta1out/v p8_2/int0 p7_1/rxd2/scl2/ta0in/tb5in (1) p8_3/int1 p8_5/nmi/sd (1) p9_7/adtrg/sin4 p9_0/tb0in/clk3 p7_0/txd2/sda2/ta0out (1) p8_4/int2/zp p7_3/cts2/rts2/ta1in/v p7_5/ta2in/w p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 p5_6/ale p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd p5_7/rdy/clkout p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p5_0/wrl/wr p5_1/wrh/bhe p1_4/d12 p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 vcc2 vss p1_5/int3/d13 p1_6/int4/d14 p1_7/int5/d15 p7_6/ta3out/txd5/sda5 p7_7/ta3in/clk5 p8_0/ta4out/u/rxd5/scl5 p8_1/ta4in/u/cts5/rts5 p1_0/cts6/rts6/d8 p1_1/clk6/d9 p1_2/rxd6/scl6/d10 p1_3/txd6/sda6/d11 p4_5/clk7/cs1 p4_6/rxd7/scl7/cs2 p4_7/txd7/sda7/cs3 p4_4/cts7/rts7/cs0 m16c/64 group prqp0100jd-b (100p6f-a) (top view) notes: 1. n-channel open-drain output. 2. check the position of pin 1 by referring to appendix 1, package dimensions . 3. symbols in brackets [ ] repres ent a functional signal as a whole. p3_0/a8 [a8/d7] p2_0/an2_0/a0, [a0/d0], a0 p2_1/an2_1/a1, [a1/d1], [a1/d0] p2_2/an2_2/a2, [a2/d2], [a2/d1] p2_3/an2_3/a3, [a3/d3], [a3/d2] p2_4/int6/an2_4/a4, [a4/d4], [a4/d3] p2_5/int7/an2_5/a5, [a5/d5], [a5/d4] p2_7/an2_7/a7, [a7/d7], [a7/d6] (3) p2_6/an2_6/a6, [a6/d6], [a6/d5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 vcc2 ports vcc1 ports rej09b0392-0064 rev.0.64 oct 12, 2007 page 8 of 373 m16c/64 group 1. overview under development preliminary specification specification in this preliminary version is subject to change. figure 1.5 pin assignment (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/cts6/rts6/d8 p1_1/clk6/d9 p1_2/rxd6/scl6/d10 vref avss avcc p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_5/anex0/clk4 p9_6/anex1/sout4 p9_7/adtrg/sin4 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 m16c/64 group plqp0100kb-a (100p6q-a) (top view) p1_3/txd6/sda6/d11 p1_4/d12 p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 vcc2 vss p1_5/int3/d13 p1_6/int4/d14 p1_7/int5/d15 p4_2/a18 p4_3/a19 p5_6/ale p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd p5_7/rdy/clkout p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p5_0/wrl/wr p5_1/wrh/bhe p7_2/clk2/ta1out/v p7_1/rxd2/scl2/ta0in/tb5in (1) p7_0/txd2/sda2/ta0out (1) vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p7_4/ta2out/w p9_3/da0/tb3in p9_4/da1/tb4in p9_1/tb1in/sin3 p9_2/tb2in/sout3 p8_2/int0 p8_3/int1 p8_5/nmi/sd (1) p9_0/tb0in/clk3 p8_4/int2/zp p7_5/ta2in/w p7_3/cts2/rts2/ta1in/v p7_6/ta3out/txd5/sda5 p7_7/ta3in/clk5 p8_0/ta4out/u/rxd5/scl5 p8_1/ta4in/u/cts5/rts5 p4_5/clk7/cs1 p4_6/rxd7/scl7/cs2 p4_7/txd7/sda7/cs3 p4_4/cts7/rts7/cs0 p3_0/a8 [a8/d7] p2_0/an2_0/a0, [a0/d0], a0 p2_1/an2_1/a1, [a1/d1], [a1/d0] p2_2/an2_2/a2, [a2/d2], [a2/d1] p2_3/an2_3/a3, [a3/d3], [a3/d2] p2_4/int6/an2_4/a4, [a4/d4], [a4/d3] p2_5/int7/an2_5/a5, [a5/d5], [a5/d4] p2_6/an2_6/a6, [a6/d6], [a6/d5] p2_7/an2_7/a7, [a7/d7], [a7/d6] notes: 1. n-channel open-drain output. 2. check the position of pin 1 by referring to appendix 1, package dimensions . 3. symbols in brackets [ ] represent a functional signal as a whole. vcc1 ports vcc2 ports (3) rej09b0392-0064 rev.0.64 oct 12, 2007 page 9 of 373 m16c/64 group 1. overview under development preliminary specification specification in this preliminary version is subject to change. table 1.4 pin names, for 100-pin package(1) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin fa fb 1 99 p9_6 sout4 anex1 2 100 p9_5 clk4 anex0 3 1 p9_4 tb4in da1 4 2 p9_3 tb3in da0 5 3 p9_2 tb2in sout3 64 p9_1 tb1in sin3 7 5 p9_0 tb0in clk3 8 6 byte 97cnvss 10 8 xcin p8_7 11 9 xcout p8_6 12 10 reset 13 11 xout 14 12 vss 15 13 xin 16 14 vcc1 17 15 p8_5 nmi sd 18 16 p8_4 int2 zp 19 17 p8_3 int1 20 18 p8_2 int0 21 19 p8_1 ta4in/ ucts5 / rts5 22 20 p8_0 ta4out/u rxd5/scl5 23 21 p7_7 ta3in clk5 24 22 p7_6 ta3out txd5/sda5 25 23 p7_5 ta2in/ w 26 24 p7_4 ta2out/w 27 25 p7_3 ta1in/ vcts2 / rts2 28 26 p7_2 ta1out/v clk2 29 27 p7_1 ta0in/tb5in rxd2/scl2 30 28 p7_0 ta0out txd2/sda2 31 29 p6_7 txd1/sda1 32 30 p6_6 rxd1/scl1 33 31 p6_5 clk1 34 32 p6_4 cts1 / rts1 / cts0 / clks1 35 33 p6_3 txd0/sda0 36 34 p6_2 rxd0/scl0 37 35 p6_1 clk0 38 36 p6_0 cts0 / rts0 39 37 p5_7 rdy /clkout 40 38 p5_6 ale 41 39 p5_5 hold 42 40 p5_4 hlda 43 41 p5_3 bclk 44 42 p5_2 rd 45 43 p5_1 wrh / bhe 46 44 p5_0 wrl / wr 47 45 p4_7 txd7/sda7 cs3 48 46 p4_6 rxd7/scl7 cs2 49 47 p4_5 clk7 cs1 50 48 p4_4 cts7 / rts7 cs0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 10 of 373 m16c/64 group 1. overview under development preliminary specification specification in this preliminary version is subject to change. table 1.5 pin names for 100-pin package(2) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin fa fb 51 49 p4_3 a19 52 50 p4_2 a18 53 51 p4_1 a17 54 52 p4_0 a16 55 53 p3_7 a15 56 54 p3_6 a14 57 55 p3_5 a13 58 56 p3_4 a12 59 57 p3_3 a11 60 58 p3_2 a10 61 59 p3_1 a9 62 60 vcc2 63 61 p3_0 a8, [a8/d7] 64 62 vss 65 63 p2_7 an2_7 a7, [a7/d7], [a7/d6] 66 64 p2_6 an2_6 a6, [a6/d6], [a6/d5] 67 65 p2_5 int7 an2_5 a5, [a5/d5], [a5/d4] 68 66 p2_4 int6 an2_4 a4, [a4/d4], [a4/d3] 69 67 p2_3 an2_3 a3, [a3/d3], [a3/d2] 70 68 p2_2 an2_2 a2, [a2/d2], [a2/d1] 71 69 p2_1 an2_1 a1, [a1/d1], [a1/d0] 72 70 p2_0 an2_0 a0, [a0/d0], a0 73 71 p1_7 int5 d15 74 72 p1_6 int4 d14 75 73 p1_5 int3 d13 76 74 p1_4 d12 77 75 p1_3 txd6/sda6 d11 78 76 p1_2 rxd6/scl6 d10 79 77 p1_1 clk6 d9 80 78 p1_0 cts6 / rts6 d8 81 79 p0_7 an0_7 d7 82 80 p0_6 an0_6 d6 83 81 p0_5 an0_5 d5 84 82 p0_4 an0_4 d4 85 83 p0_3 an0_3 d3 86 84 p0_2 an0_2 d2 87 85 p0_1 an0_1 d1 88 86 p0_0 an0_0 d0 89 87 p10_7 ki3 an7 90 88 p10_6 ki2 an6 91 89 p10_5 ki1 an5 92 90 p10_4 ki0 an4 93 91 p10_3 an3 94 92 p10_2 an2 95 93 p10_1 an1 96 94 avss 97 95 p10_0 an0 98 96 vref 99 97 avcc 100 98 p9_7 sin4 adtrg rej09b0392-0064 rev.0.64 oct 12, 2007 page 11 of 373 m16c/64 group 1. overview under development preliminary specification specification in this preliminary version is subject to change. 1.6 pin functions note: 1. vcc1 is hereinafter referred to as vcc unless otherwise noted. table 1.6 pin functions (1) signal name pin name i/o power supply description power supply input vcc1 vcc2 vss i - apply 2.7 to 5.5 v to pins vcc1 and vcc2 (vcc1 = vcc2) and 0 v to the vss pin (1) analog power supply input avcc avss i vcc1 apply the power supply for the a/d converter. connect the avcc pin to vcc1. connect the avss pin to vss. reset input reset i vcc1 low active input pin. driving this pin low resets the mcu. cnvss cnvss i vcc1 input pin to switch processor mode. to start up in single-chip mode after a reset, connect the cnvss pin to vss via resister. to start up in microprocessor mode, connect the cnvss pin to vss1. external data bus width select input byte i vcc1 input pin to select the data bus of the external memory area. the data bus is 16-bit when it is low and 8-bit when it is high. this pin must be fixed either high or low. connect the byte pin to vss in single-chip mode bus control pins d0 to d7 i/o vcc2 inputs or outputs data (d0 to d7) while accessing an exter- nal memory area with separate bus d8 to d15 i/o vcc2 inputs or outputs data (d8 to d15) while accessing an exter- nal memory area with 16-bit separate bus a0 to a19 o vcc2 outputs address bits a0 to a19 a0/d0 to a7/d7 i/o vcc2 inputs or outputs data (d0 to d7) and outputs address bits (a0 to a7) by timesharing, while accessing an external mem- ory area with 8-bit multiplexed bus a1/d0 to a8/d7 i/o vcc2 inputs or outputs data (d0 to d7) and outputs address bits (a1 to a8) by timesharing, while accessing an external mem- ory area with 16-bit multiplexed bus cs0 to cs3 o vcc2 outputs chip-select signals cs0 to cs3 to specify an exter- nal memory area wrl / wr wrh / bhe rd o vcc2 low active output pins. outputs wrl , wrh , ( wr , bhe) , rd signals. wrl and wrh can be switched with or bhe and wr can be selected by a program. wrl , wrh and rd selected if the external data bus is 16-bit, data is written to an even address in external memory area when wrl is driven low. data is written to an odd address when wrh is driven low. data is read when rd is driven low. wr , bhe and rd are selected data is written to external memory area when wr is driven low. data in external memory area is read when rd is driven low. an odd address is accessed when bhe is driven low. select wr , bhe , and rd for external 8-bit data bus ale o vcc2 output ale signal to latch address. hold i vcc2 low active input pin. the mcu is placed in hold state while the hold pin is driven low. hlda o vcc2 low active output pin. in a hold state, hlda outputs a low- level signal. rdy i vcc2 low active input pin. the mcu is placed in wait state while the rdy pin is driven low. power supply: vcc2 is used to supply power to external bus related pins. rej09b0392-0064 rev.0.64 oct 12, 2007 page 12 of 373 m16c/64 group 1. overview under development preliminary specification specification in this preliminary version is subject to change. notes: 1. consult the oscillator manufacturer regarding the oscillation characteristics. 2. txd2, sda2, and scl2 are n-channel open-drain output pi ns. txdi (i = 0, 1, 5 to 7), sdai, and scli can be selected as cmos output pins or n-chan nel open-drain output pins by a program. table 1.7 pin functions (2) signal name pin name i/o power supply description main clock input xin i vcc1 i/o pins for th e main clock oscillation circuit. connect a ceramic resonator or crystal oscillator between xin and xout (1) . to apply an external clock, connect it to xin and leave xout open. main clock output xout o vcc1 sub clock input xcin i vcc1 i/o pins for a sub clock oscillation circuit. connect a crystal oscillator between xcin and xcout (1). to apply an external clock, connect it to xcin and leave xcout open sub clock output xcout o vcc1 bclk output bclk o vcc2 output pin for bclk signal clock output clkout o vcc2 this pin outputs the clock having the same frequency as fc, f8, or f32 int interrupt input int0 to int2 i vcc1 low active input pins for int interrupt int3 to int7 i vcc2 nmi interrupt input nmi i vcc1 low active input pin for nmi interrupt key input interrupt input ki0 to ki3 i vcc1 low active input pins for key input interrupt timer a ta0out to ta4out i/o vcc1 timer a0 to a4 i/o pins (ta0out as an output pin is n-channel open drain output) ta0in to ta4in i vcc1 timer a0 to a4 input pins zp i vcc1 input pin for z-phase timer b tb0in to tb5in i vcc1 timer b0 to b5 input pins three-phase motor control timer u, u , v, v , w, w o vcc1 output pins for three-phase motor control timer output sd i vcc1 input pin for three-phase motor control timer input serial interface uart0 to uart2, uart5 to uart7 cts0 to cts2 , cts5 i vcc1 input pins to control data transmission cts6 , cts7 i vcc2 rts0 to rts2 , rts5 o vcc1 output pins to control data reception rts6 , rts7 o vcc2 clk0 to clk2, clk5 i/o vcc1 transfer clock i/o pins clk6, clk7 i/o vcc2 rxd0 to rxd2 , rxd5 i vcc1 serial data input pins rxd6, rxd7 i vcc2 txd0 to txd2 , txd5 o vcc1 serial data output pins (2) txd6, txd7 o vcc2 clks1 o vcc1 output pin for transfer clock multiple-pin output func- tion rej09b0392-0064 rev.0.64 oct 12, 2007 page 13 of 373 m16c/64 group 1. overview under development preliminary specification specification in this preliminary version is subject to change. note: 1. txd2, sda2, and scl2 are n-channel open drain output pins. txdi (i = 0, 1, 5 to 7), sdai, scli can be selected as cmos output pin or n-channel open drain output pin by program. table 1.8 pin functions (3) signal name pin name i/o power sup- ply description uart0 to uart2, uart5 to uart7 i 2 c mode sda0 to sda2, sda5 i/o vcc1 serial data i/o pins (1) sda6, sda7 i/o vcc2 scl0 to scl2, scl5 i/o vcc1 transfer clock i/o pins (1) scl6, scl7 i/o vcc2 serial interface si/03, si/04 clks3, clks4 i/o vcc1 transfer clock i/o pins sin3, sin4 i vcc1 serial data input pins sout3, sout4 o vcc1 serial data output pins reference voltage input vref i vcc1 reference voltage input pins for the a/d converter and d/a converter. connect to vcc1. a/d converter an0 to an7 i vcc1 analog input pins for the a/d converter an0_0 to an0_7 an2_0 to an2_7 i vcc2 adtrg i vcc1 input pin for an external a/d trigger anex0, anex1 i vcc1 extended analog input pin for the a/d converter d/a converter da0, da1 o vcc1 output pin for the d/a converter i/o port p0_0 to p0_7 p1_0 to p1_7 p2_0 to p2_7 p3_0 to p3_7 p4_0 to p4_7 p5_0 to p5_7 i/o vcc2 8-bit cmos i/o ports. a direction register determines whether each pin is used as an input port or an output port. a pull-up resistor may be enabled or disabled for input ports in 4-bit units. p6_0 to p6_7 p7_0 to p7_7 p8_0 to p8_7 p9_0 to p9_7 p10_0 to p10_7 i/o vcc1 8-bit i/o ports having equivalent functions to p0. however, p7_0, p7_1, and p8_5 are n-channel open-drain output ports. no pull-up resistor is provided. p8_5 is an input port for verifying the nmi pin level and shares a pin with nmi. rej09b0392-0064 rev.0.64 oct 12, 2007 page 14 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 2. central processing unit (cpu) 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. seven registers (r 0, r1, r2, r3, a0, a1, and fb) out of thirteen regis- ters configure a register bank. ther e are two sets of register banks. figure 2.1 central processing unit register 2.1 data registers (r0, r1, r2 and r3) the r0, r1, r2, and r3 are 16-bit registers used for transfer, arithmetic and logic operations. r0 and r1 can be split into high-order (r0h/r1h) and low-order bi ts (r0l/r1l) to be used separately as 8-bit data registers. r0 can be combined with r2 and used as a 32-bit data register (r2r0). the same applies to r3r1. r0h (high order bits of r0) b15 b8 b7 b0 r3 intbh usp isp sb note: 1. these registers comprise a register bank. there are two sets of register banks. c d z s b o i u ipl r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc intbh is 4 high-order bits of intb register and intbl is 16 low-order bits of intb register b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 address registers (1) frame base registers (1) program counter interrupt table register data registers (1) user stack pointer interrupt stack pointer static base register flag register reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level r1h (high order bits of r1) r0l (low order bits of r0) r1l (low order bits of r1) rej09b0392-0064 rev.0.64 oct 12, 2007 page 15 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 2. central processing unit (cpu) 2.2 address registers (a0 and a1) a0 and a1 are 16-bit registers used for a0-/a1-indir ect addressing, a0-/a1-relative addressing, transfer, arithmetic and logic operations. a0 can be combined with a1 and used as a 32-bit address register (a1a0). 2.3 frame base registers (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register indicating the start address of an relocatable interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) the stack pointers (sp), as usp and isp, are each 16 bits wide. the u flag is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register used for sb-relative addressing. 2.8 flag register (flg) flg is a 11-bit register indicating the cpu state. 2.8.1 carry flag (c flag) the c flag retains a carry, borrow, or shift-out bit th at has been generated by the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is for debugging purpose only. set it to 0. 2.8.3 zero flag (z flag) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s flag) the s flag is set to 1 when an arithmetic oper ation results in a negative value; otherwise to 0. 2.8.5 register bank se lect flag (b flag) register bank 0 is selected when the b flag is set to 0. register bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o flag) the o flag is set to 1 when an arithmetic oper ation results in an overflow; otherwise to 0. 2.8.7 interrupt enable flag (i flag) the i flag enables maskable interrupts. maskable interrupts are disabled when the i flag is set to 0, and enabled when it is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. rej09b0392-0064 rev.0.64 oct 12, 2007 page 16 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 2. central processing unit (cpu) 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt r equest is acknowledged or the int instruction of soft- ware interrupt number 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interr upt priority levels fr om level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved space only write 0 to bits assigned as reserved bits. the read value is undefined. rej09b0392-0064 rev.0.64 oct 12, 2007 page 17 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 3. memory 3. memory figure 3.1 is a memory map of the m16c/64 group. the m16c/64 group has 1 mbyte address space from address 00000h to fffffh. the internal rom is flash memory. program rom 1 is allocated from address fffffh to lower. for example, a 64-kbyte program rom 1 is addressed from f0000h to fffffh. an 8-kbyte data flash is addressed from 0e000h to 0ffffh. this data flash space is used not only for data storage but also for pro- gram storage. program rom 2 is allocated addresses 10000h to 13fffh. the user boot code area is assigned addresses 13ff0h to 13fffh in the program rom 2. the fixed interrupt vectors are addr essed from fffdch to fffffh. they store the starting address of each interrupt routine. the internal ram is allocated from address 00400h to higher. for example, a 10-kbyte internal ram is addressed from 00400h to 02bffh. the internal ram is used not only for data storage but also for stack area when subroutines are called or when interrupt request are acknowledged. sfrs are allocated from address 00000h to 003ffh and from 0d000h to 0d7ffh. peripheral function con- trol registers are located here. all blank spaces within sfrs are reserved and cannot be accessed by users. the special page vectors are addressed from ffe00h to fffd7h. they are used for the jmps instruction and jsrs instruction. refer to the m16c/60, m16c/20 series software manual for details. in memory expansion mode or microprocessor mode, some spaces are reserved and cannot be accessed by users. figure 3.1 memory map notes: 1. this memory map is based on the case that the pm10 bit in the pm1 register is 1, the pm13 bit in the pm1 register is 1, and the prg2c0 bit in the prg2c register is 0. 2. available as external area in microprocessor mode. internal ram reserved area 00000h xxxxxh 0d000h sfr 00400h sfr 0d800h internal rom (data flash) 0e000h internal rom (program rom 2) 10000h external area reserved area (2) internal rom (program rom 1) 14000h 80000h yyyyyh fffffh reserved area 28000h 27000h reset watchdog timer single step address match brk instruction overflow undefined instruction special page vector table fffffh fffdch ffe00h dbc nmi size address yyyyyh size address xxxxxh internal ram internal rom 128 kbytes e0000h 12 kbytes 033ffh 256 kbytes c0000h 16 kbytes 043ffh 512 kbytes 80000h 31 kbytes 07fffh reserved area external area external area fffd8h 13fffh 13ff0h user boot code area rej09b0392-0064 rev.0.64 oct 12, 2007 page 18 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) 4. special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tables 4.1 to 4.14 list sfr information. notes: x: undefined 1. the blank areas are reserved and cannot be accessed by users. 2. software reset, watchdog timer reset, and oscillation stop dete ction reset do not affect bits pm01 and pm00 in the pm0 regist er, and registers vcr1, vcr2, and vw0c. 3. oscillation stop detection reset do no t affect bits cm20, cm21, and cm27. 4. the cwr bit in the rstfr register is set to 0 after br own-out reset. this bit does not change by any other reset. table 4.1 sfr information (1) ( 1) address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00000000b (cnvss pin is ?l?) 00000011b(cnvss pin is ?h?) (2) 0005h processor mode register 1 pm1 00001000b 0006h system clock control register 0 cm0 01001000b 0007h system clock control register 1 cm1 00100000b 0008h chip select control register csr 00000001b 0009h 000ah protect register prcr 00h 000bh data bank register dbr 00h 000ch oscillation stop detection register cm2 0x000010b ( 3) 000dh 000eh 000fh 0010h program 2 area control register prg2c xxxxxxx0b 0011h 0012h peripheral clock select register pclkr 00000011b 0013h 0014h 0015h clock prescaler reset flag cpsrf 0xxxxxxxb 0016h 0017h 0018h reset source determine flag rstfr 0xxxxxxxb ( 4) 0019h voltage detection 2 circuit flag register vcr1 00001000b ( 2) 001ah voltage detection circuit operation enable register vcr2 000x0000b (hardware reset 1) 001x0000b (brown-out reset) ( 2) 001bh chip select expansion control register cse 00h 001ch pll control register 0 plc0 0x01x010b 001dh 001eh processor mode register 2 pm2 xxx00x01b ( 2) 001fh low voltage detection interrupt register d4int 00h 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002ah voltage monitor 0 circuit control register vw0c 10001x10b ( hardware reset 1) 11001x11b (brown-out reset) ( 2) 002bh 002ch 002dh 002eh 002fh rej09b0392-0064 rev.0.64 oct 12, 2007 page 19 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) note: x: undefined 1. the blank areas are reserved and cannot be accessed by users. table 4.2 sfr information (2) ( 1) address register symbol after reset 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh 0040h 0041h 0042h int7 interrupt control register int7ic xx00x000b 0043h int6 interrupt control register int6ic xx00x000b 0044h int3 interrupt control register int3ic xx00x000b 0045h timer b5 interrupt control register tb5ic xxxxx000b 0046h timer b4 interrupt control register, uart1 bus collision detection interrupt control register tb4ic, u1bcnic xxxxx000b 0047h timer b3 interrupt control register, uart0 bus collision detection interrupt control register tb3ic, u0bcnic xxxxx000b 0048h si/o4 interrupt control register, int5 interrupt control register s4ic, int5ic xx00x000b 0049h si/o3 interrupt control register, int4 interrupt control register s3ic, int4ic xx00x000b 004ah uart2 bus collision detection interrupt control register bcnic xxxxx000b 004bh dma0 interrupt control register dm0ic xxxxx000b 004ch dma1 interrupt control register dm1ic xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh uart2 transmit interrupt control register s2tic xxxxx000b 0050h uart2 receive interrupt control register s2ric xxxxx000b 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h timer a0 interrupt control register ta0ic xxxxx000b 0056h timer a1 interrupt control register ta1ic xxxxx000b 0057h timer a2 interrupt control register ta2ic xxxxx000b 0058h timer a3 interrupt control register ta3ic xxxxx000b 0059h timer a4 interrupt control register ta4ic xxxxx000b 005ah timer b0 interrupt control register tb0ic xxxxx000b 005bh timer b1 interrupt control register tb1ic xxxxx000b 005ch timer b2 interrupt control register tb2ic xxxxx000b 005dh int0 interrupt control register int0ic xx00x000b 005eh int1 interrupt control register int1ic xx00x000b 005fh int2 interrupt control register int2ic xx00x000b rej09b0392-0064 rev.0.64 oct 12, 2007 page 20 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) note: x: undefined 1. the blank areas are reserved and cannot be accessed by users. table 4.3 sfr information (3) ( 1) address register symbol after reset 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h dma2 interrupt control register dm2ic xxxxx000b 006ah dma3 interrupt control register dm3ic xxxxx000b 006bh uart5 bus collision detection interrupt control register u5bcnic xxxxx000b 006ch uart5 transmit interrupt control register s5tic xxxxx000b 006dh uart5 receive interrupt control register s5ric xxxxx000b 006eh uart6 bus collision detection interrupt control register u6bcnic xxxxx000b 006fh uart6 transmit interrupt control register s6tic xxxxx000b 0070h uart6 receive interrupt control register s6ric xxxxx000b 0071h uart7 bus collision detection interrupt control register u7bcnic xxxxx000b 0072h uart7 transmit interrupt control register s7tic xxxxx000b 0073h uart7 receive interrupt control register s7ric xxxxx000b 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh to 015fh rej09b0392-0064 rev.0.64 oct 12, 2007 page 21 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) note: x: undefined 1. the blank areas are reserved and cannot be accessed by users. table 4.4 sfr information (4) ( 1) address register symbol after reset 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh 0180h dma0 source pointer sar0 xxh 0181h xxh 0182h 0xh 0183h 0184h dma0 destination pointer dar0 xxh 0185h xxh 0186h 0xh 0187h 0188h dma0 transfer counter tcr0 xxh 0189h xxh 018ah 018bh 018ch dma0 control register dm0con 00000x00b 018dh 018eh 018fh 0190h dma1 source pointer sar1 xxh 0191h xxh 0192h 0xh 0193h 0194h dma1 destination pointer dar1 xxh 0195h xxh 0196h 0xh 0197h 0198h dma1 transfer counter tcr1 xxh 0199h xxh 019ah 019bh 019ch dma1 control register dm1con 00000x00b 019dh 019eh 019fh rej09b0392-0064 rev.0.64 oct 12, 2007 page 22 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) note: x: undefined 1. the blank areas are reserved and cannot be accessed by users. table 4.5 sfr information (5) ( 1) address register symbol after reset 01a0h dma2 source pointer sar2 xxh 01a1h xxh 01a2h 0xh 01a3h 01a4h dma2 destination pointer dar2 xxh 01a5h xxh 01a6h 0xh 01a7h 01a8h dma2 transfer counter tcr2 xxh 01a9h xxh 01aah 01abh 01ach dma2 control register dm2con 00000x00b 01adh 01aeh 01afh 01b0h dma3 source pointer sar3 xxh 01b1h xxh 01b2h 0xh 01b3h 01b4h dma3 destination pointer dar3 xxh 01b5h xxh 01b6h 0xh 01b7h 01b8h dma3 transfer counter tcr3 xxh 01b9h xxh 01bah 01bbh 01bch dma3 control register dm3con 00000x00b 01bdh 01beh 01bfh 01c0h 01c1h 01c2h 01c3h 01c4h 01c5h 01c6h 01c7h 01c8h timer b count source select register 0 tbcs0 00h 01c9h timer b count source select register 1 tbcs1 x0h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h timer a count source select register 0 tacs0 00h 01d1h timer a count source select register 1 tacs1 00h 01d2h timer a count source select register 2 tacs2 x0h 01d3h 01d4h 01d5h timer a waveform output function select register tapofs xxx00000b 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh rej09b0392-0064 rev.0.64 oct 12, 2007 page 23 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) note: x: undefined 1. the blank areas are reserved and cannot be accessed by users. table 4.6 sfr information (6) ( 1) address register symbol after reset 01e0h 01e1h 01e2h 01e3h 01e4h 01e5h 01e6h 01e7h 01e8h timer b count source select register 2 tbcs2 00h 01e9h timer b count source select register 3 tbcs3 x0h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h 01f1h 01f2h 01f3h 01f4h 01f5h 01f6h 01f7h 01f8h 01f9h 01fah 01fbh 01fch 01fdh 01feh 01ffh 0200h 0201h 0202h 0203h 0204h 0205h interrupt source select register 3 ifsr3a 00h 0206h interrupt source select register 2 ifsr2a 00h 0207h interrupt source select register ifsr 00h 0208h 0209h 020ah 020bh 020ch 020dh 020eh address match interrupt enable register aier xxxxxx00b 020fh address match interrupt enable register 2 aier2 xxxxxx00b 0210h address match interrupt register 0 rmad0 00h 0211h 00h 0212h x0h 0213h 0214h address match interrupt register 1 rmad1 00h 0215h 00h 0216h x0h 0217h 0218h address match interrupt register 2 rmad2 00h 0219h 00h 021ah x0h 021bh 021ch address match interrupt register 3 rmad3 00h 021dh 00h 021eh x0h 021fh rej09b0392-0064 rev.0.64 oct 12, 2007 page 24 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) note: x: undefined 1. the blank areas are reserved and cannot be accessed by users. table 4.7 sfr information (7) (1) address register symbol after reset 0220h flash memory control register 0 fmr0 00000001b 0221h flash memory control register 1 fmr1 00x0xx0xb 0222h flash memory control register 2 fmr2 xxxx0000b 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022ah 022bh 022ch 022dh 022eh 022fh 0230h flash memory control register 6 fmr6 xx0xxx00b 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023ah 023bh 023ch 023dh 023eh 023fh 0240h 0241h 0242h 0243h 0244h uart0 special mode register 4 u0smr4 00h 0245h uart0 special mode register 3 u0smr3 000x0x0xb 0246h uart0 special mode register 2 u0smr2 x0000000b 0247h uart0 special mode register u0smr x0000000b 0248h uart0 transmit/receive mode register u0mr 00h 0249h uart0 bit rate register u0brg xxh 024ah uart0 transmit buffer register u0tb xxh 024bh xxh 024ch uart0 transmit/receive control register 0 u0c0 00001000b 024dh uart0 transmit/receive control register 1 u0c1 00xx0010b 024eh uart0 receive buffer register u0rb xxh 024fh xxh 0250h uart transmit/receive control register 2 ucon x0000000b 0251h 0252h 0253h 0254h uart1 special mode register 4 u1smr4 00h 0255h uart1 special mode register 3 u1smr3 000x0x0xb 0256h uart1 special mode register 2 u1smr2 x0000000b 0257h uart1 special mode register u1smr x0000000b 0258h uart1 transmit/receive mode register u1mr 00h 0259h uart1 bit rate register u1brg xxh 025ah uart1 transmit buffer register u1tb xxh 025bh xxh 025ch uart1 transmit/receive control register 0 u1c0 00001000b 025dh uart1 transmit/receive control register 1 u1c1 00xx0010b 025eh uart1 receive buffer register u1rb xxh 025fh xxh rej09b0392-0064 rev.0.64 oct 12, 2007 page 25 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) note: x: undefined 1. the blank areas are reserved and cannot be accessed by users. table 4.8 sfr information (8) ( 1) address register symbol after reset 0260h 0261h 0262h 0263h 0264h uart2 special mode register 4 u2smr4 00h 0265h uart2 special mode register 3 u2smr3 000x0x0xb 0266h uart2 special mode register 2 u2smr2 x0000000b 0267h uart2 special mode register u2smr x0000000b 0268h uart2 transmit/receive mode register u2mr 00h 0269h uart2 bit rate register u2brg xxh 026ah uart2 transmit buffer register u2tb xxh 026bh xxh 026ch uart2 transmit/receive control register 0 u2c0 00001000b 026dh uart2 transmit/receive control register 1 u2c1 00000010b 026eh uart2 receive buffer register u2rb xxh 026fh xxh 0270h si/o3 transmit/receive register s3trr xxh 0271h 0272h si/o3 control register s3c 01000000b 0273h si/o3 bit rate register s3brg xxh 0274h si/o4 transmit/receive register s4trr xxh 0275h 0276h si/o4 control register s4c 01000000b 0277h si/o4 bit rate register s4brg xxh 0278h si/o34 control register 2 s34c2 00xxx0x0b 0279h 027ah 027bh 027ch 027dh 027eh 027fh 0280h 0281h 0282h 0283h 0284h uart5 special mode register 4 u5smr4 00h 0285h uart5 special mode register 3 u5smr3 000x0x0xb 0286h uart5 special mode register 2 u5smr2 x0000000b 0287h uart5 special mode register u5smr x0000000b 0288h uart5 transmit/receive mode register u5mr 00h 0289h uart5 bit rate register u5brg xxh 028ah uart5 transmit buffer register u5tb xxh 028bh xxh 028ch uart5 transmit/receive control register 0 u5c0 00001000b 028dh uart5 transmit/receive control register 1 u5c1 00000010b 028eh uart5 receive buffer register u5rb xxh 028fh xxh 0290h 0291h 0292h 0293h 0294h uart6 special mode register 4 u6smr4 00h 0295h uart6 special mode register 3 u6smr3 000x0x0xb 0296h uart6 special mode register 2 u6smr2 x0000000b 0297h uart6 special mode register u6smr x0000000b 0298h uart6 transmit/receive mode register u6mr 00h 0299h uart6 bit rate register u6brg xxh 029ah uart6 transmit buffer register u6tb xxh 029bh xxh 029ch uart6 transmit/receive control register 0 u6c0 00001000b 029dh uart6 transmit/receive control register 1 u6c1 00000010b 029eh uart6 receive buffer register u6rb xxh 029fh xxh rej09b0392-0064 rev.0.64 oct 12, 2007 page 26 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) note: x: undefined 1. the blank areas are reserved and cannot be accessed by users. table 4.9 sfr information (9) ( 1) address register symbol after reset 02a0h 02a1h 02a2h 02a3h 02a4h uart7 special mode register 4 u7smr4 00h 02a5h uart7 special mode register 3 u7smr3 000x0x0xb 02a6h uart7 special mode register 2 u7smr2 x0000000b 02a7h uart7 special mode register u7smr x0000000b 02a8h uart7 transmit/receive mode register u7mr 00h 02a9h uart7 bit rate register u7brg xxh 02aah uart7 transmit buffer register u7tb xxh 02abh xxh 02ach uart7 transmit/receive control register 0 u7c0 00001000b 02adh uart7 transmit/receive control register 1 u7c1 00000010b 02aeh uart7 receive buffer register u7rb xxh 02afh xxh 02b0h 02b1h 02b2h 02b3h 02b4h 02b5h 02b6h 02b7h 02b8h 02b9h 02bah 02bbh 02bch 02bdh 02beh 02bfh 02c0h 02c1h 02c2h 02c3h 02c4h 02c5h 02c6h 02c7h 02c8h 02c9h 02cah 02cbh 02cch 02cdh 02ceh 02cfh 02d0h 02d1h 02d2h 02d3h 02d4h 02d5h 02d6h 02d7h 02d8h 02d9h 02dah 02dbh 02dch 02ddh 02deh 02dfh rej09b0392-0064 rev.0.64 oct 12, 2007 page 27 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) note: x: undefined 1. the blank areas are reserved and cannot be accessed by users. table 4.10 sfr information (10) ( 1) address register symbol after reset 02e0h 02e1h 02e2h 02e3h 02e4h 02e5h 02e6h 02e7h 02e8h 02e9h 02eah 02ebh 02ech 02edh 02eeh 02efh 02f0h 02f1h 02f2h 02f3h 02f4h 02f5h 02f6h 02f7h 02f8h 02f9h 02fah 02fbh 02fch 02fdh 02feh 02ffh 0300h timer b3,4,5 count start flag tbsr 000xxxxxb 0301h 0302h timer a1-1 register ta11 xxh 0303h xxh 0304h timer a2-1 register ta21 xxh 0305h xxh 0306h timer a4-1 register ta41 xxh 0307h xxh 0308h three-phase pwm control register 0 invc0 00h 0309h three-phase pwm control register 1 invc1 00h 030ah three-phase output buffer register 0 idb0 xx 111111b 030bh three-phase output buffer register 1 idb1 xx 111111b 030ch dead time timer dtt xxh 030dh timer b2 interrupt generation frequency set counter ictb2 xxh 030eh 030fh 0310h timer b3 register tb3 xxh 0311h xxh 0312h timer b4 register tb4 xxh 0313h xxh 0314h timer b5 register tb5 xxh 0315h xxh 0316h 0317h 0318h 0319h 031ah 031bh timer b3 mode register tb3mr 00xx0000b 031ch timer b4 mode register tb4mr 00xx0000b 031dh timer b5 mode register tb5mr 00xx0000b 031eh 031fh rej09b0392-0064 rev.0.64 oct 12, 2007 page 28 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) note: x: undefined 1. the blank areas are reserved and cannot be accessed by users. table 4.11 sfr information (11) ( 1) address register symbol after reset 0320h count start flag tabsr 00h 0321h 0322h one-shot start flag onsf 00h 0323h trigger select register trgsr 00h 0324h up/down flag udf 00h 0325h 0326h timer a0 register ta0 xxh 0327h xxh 0328h timer a1 register ta1 xxh 0329h xxh 032ah timer a2 register ta2 xxh 032bh xxh 032ch timer a3 register ta3 xxh 032dh xxh 032eh timer a4 register ta4 xxh 032fh xxh 0330h timer b0 register tb0 xxh 0331h xxh 0332h timer b1 register tb1 xxh 0333h xxh 0334h timer b2 register tb2 xxh 0335h xxh 0336h timer a0 mode register ta0mr 00h 0337h timer a1 mode register ta1mr 00h 0338h timer a2 mode register ta2mr 00h 0339h timer a3 mode register ta3mr 00h 033ah timer a4 mode register ta4mr 00h 033bh timer b0 mode register tb0mr 00xx0000b 033ch timer b1 mode register tb1mr 00xx0000b 033dh timer b2 mode register tb2mr 00xx0000b 033eh timer b2 special mode register tb2sc xxxxxx00b 033fh 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034ah 034bh 034ch 034dh 034eh 034fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035ah 035bh 035ch 035dh 035eh 035fh rej09b0392-0064 rev.0.64 oct 12, 2007 page 29 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) notes: x: undefined 1. the blank areas are reserved and cannot be accessed by users. 2. values after hardware reset 1 or brown-out reset are as follows: ? 00000000b when "l" is input to the cnvss pin ? 00000010b when "h" is input to the cnvss pin values after software reset, watchdog timer reset, and oscillation stop detection reset are as follows: ? 00000000b when bits pm01 and pm00 in the pm0 register are set to 00b (single-chip mode). ? 00000010b when bits pm01 and pm00 in the pm0 register are set to 01b (memory expansion mode) or 11b (microprocessor mode). 3. when the csproint bit in the ofs1 address is set to 0, value after reset is 10000000b table 4.12 sfr information (12) ( 1) address register symbol after reset 0360h pull-up control register 0 pur0 00h 0361h pull-up control register 1 pur1 00000000b (2) 00000010b 0362h pull-up control register 2 pur2 00h 0363h 0364h 0365h 0366h port control register pcr 00000xx0bh 0367h 0368h 0369h 036ah 036bh 036ch 036dh 036eh 036fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037ah 037bh 037ch count source protection mode register cspr 00h (3) 037dh watchdog timer reset register wdtr xxh 037eh watchdog timer start register wdts xxh 037fh watchdog timer control register wdc 00xxxxxxb 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038ah 038bh 038ch 038dh 038eh 038fh rej09b0392-0064 rev.0.64 oct 12, 2007 page 30 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) note: x: undefined 1. the blank areas are reserved and cannot be accessed by users. table 4.13 sfr information (13) ( 1) address register symbol after reset 0390h dma2 source select register dm2sl 00h 0391h 0392h dma3 source select register dm3sl 00h 0393h 0394h 0395h 0396h 0397h 0398h dma0 source select register dm0sl 00h 0399h 039ah dma1 source select register dm1sl 00h 039bh 039ch 039dh 039eh 039fh 03a0h 03a1h 03a2h 03a3h 03a4h 03a5h 03a6h 03a7h 03a8h 03a9h 03aah 03abh 03ach 03adh 03aeh 03afh 03b0h 03b1h 03b2h 03b3h 03b4h 03b5h 03b6h 03b7h 03b8h 03b9h 03bah 03bbh 03bch crc data register crcd xxh 03bdh xxh 03beh crc input register crcin xxh 03bfh 03c0h a/d register 0 ad0 xxxxxxxxb 03c1h 000000xxb 03c2h a/d register 1 ad1 xxxxxxxxb 000000xxb 03c3h 03c4h a/d register 2 ad2 xxxxxxxxb 000000xxb 03c5h 03c6h a/d register 3 ad3 xxxxxxxxb 000000xxb 03c7h 03c8h a/d register 4 ad4 xxxxxxxxb 000000xxb 03c9h rej09b0392-0064 rev.0.64 oct 12, 2007 page 31 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 4. special function registers (sfrs) note: x: undefined 1. the blank areas are reserved and cannot be accessed by users. table 4.14 sfr information (14) ( 1) address register symbol after reset 03cah a/d register 5 ad5 xxxxxxxxb 000000xxb 03cbh 03cch a/d register 6 ad6 xxxxxxxxb 000000xxb 03cdh 03ceh a/d register 7 ad7 xxxxxxxxb 000000xxb 03cfh 03d0h 03d1h 03d2h 03d3h 03d4h a/d control register 2 adcon2 0000x00xb 03d5h 03d6h a/d control register 0 adcon0 00000xxxb 03d7h a/d control register 1 adcon1 0000x000b 03d8h d/a0 register da0 00h 03d9h 03dah d/a1 register da1 00h 03dbh 03dch d/a control register dacon 00h 03ddh 03deh 03dfh 03e0h port p0 register p0 xxh 03e1h port p1 register p1 xxh 03e2h port p0 direction register pd0 00h 03e3h port p1 direction register pd1 00h 03e4h port p2 register p2 xxh 03e5h port p3 register p3 xxh 03e6h port p2 direction register pd2 00h 03e7h port p3 direction register pd3 00h 03e8h port p4 register p4 xxh 03e9h port p5 register p5 xxh 03eah port p4 direction register pd4 00h 03ebh port p5 direction register pd5 00h 03ech port p6 register p6 xxh 03edh port p7 register p7 xxh 03eeh port p6 direction register pd6 00h 03efh port p7 direction register pd7 00h 03f0h port p8 register p8 xxh 03f1h port p9 register p9 xxh 03f2h port p8 direction register pd8 00h 03f3h port p9 direction register pd9 00h 03f4h port p10 register p10 xxh 03f5h 03f6h port p10 direction register pd10 00h 03f7h 03f8h 03f9h 03fah 03fbh 03fch 03fdh 03feh 03ffh d000h to d7ffh rej09b0392-0064 rev.0.64 oct 12, 2007 page 32 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 5. reset 5. reset hardware reset 1, brow n-out reset, software reset, watchdog timer reset and oscillation stop detection reset are available to reset the microcomputer. 5.1 hardware reset 1 the microcomputer resets pins, the cpu, and sfr by setting the reset pin. if the supply voltage meets the recommended operating conditions, the microcompu ter resets all pins, the cpu, and sfr when an ?l? signal is applied to the reset pin (see table 5.1 ?pin status when reset pin level is ?l?? ). when the signal applied to the reset pin changes low (?l?) to high (?h?), the microcomputer executes the program in an address indicated by the reset vector. th e 125 khz on-chip oscilla tor clock divided by 8 is automatically selected as a cpu clock after reset. refer to 4. ?special function registers (sfrs)? for sfr states after reset. the internal ram is not reset. when an ?l? signal is applied to the reset pin while writing data to the internal ram, the internal ram is in an indeterminate state. figure 5.1 shows an example reset circuit. figure 5.2 shows a reset sequence. table 5.1 lists pin sta- tus when reset pin level is ?l?. 5.1.1 reset on a stable supply voltage (1) apply ?l? to the reset pin (2) wait for 1/foco-s 20 (3) apply an ?h? signal to the reset pin 5.1.2 power-on reset (1) apply ?l? to the reset pin (2) raise the supply voltage to the recommended operating level (3) insert td(p-r) ms as wait time for the internal vo ltage to stabilize (4) wait for 1/foco-s 20 (5) apply ?h? to the reset pin figure 5.1 example reset circuit reset vcc1 reset vcc1 0v 0v recommended operation voltage td (p-r)+ x 20 or above 0.2 vcc1 or below 0.2 vcc1 or below 1 foco - s rej09b0392-0064 rev.0.64 oct 12, 2007 page 33 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 5. reset figure 5.2 reset sequence bclk address address address content of reset vector bclk 48 cycles (foco-s divided by 8 x 48) ffffch ffffdh ffffeh content of reset vector ffffch ffffeh content of reset vector ffffeh xin reset rd wr cs0 rd wr cs0 ffffch more than 20 cycles of foco-s are necessary. td(p-r) vcc1, vcc2 microprocessor mode byte = ?h? microprocessor mode byte = ?l? single-chip mode rej09b0392-0064 rev.0.64 oct 12, 2007 page 34 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 5. reset note: 1. shown here is the valid pin stat e when the internal power supply voltage has stabilized after power on. when cnvss = vcc1, the pi n state is indeterminate until the internal power su pply voltage sta- bilizes. 2. apply a ?h? signal. table 5.1 pin status when reset pin level is ?l? pin name status cnvss = vss cnvss = vcc1 (1) byte = vss byte = vcc1 p0 input port data input data input p1 input port data input input port p2, p3, p4_0 to p4_3 input port address output (undefined) address output (undefined) p4_4 input port cs0 output (?h? is output) cs0 output (?h? is output) p4_5 to p4_7 input port input port (pulled high) input port (pulled high) p5_0 input port wr output (?h? is output) wr output (?h? is output) p5_1 input port bhe output (undefined) bhe output (undefined) p5_2 input port rd output (?h? is output) rd output (?h? is output) p5_3 input port bclk output bclk output p5_4 input port hlda output (the output value depends on the input to the hold pin) hlda output (the output value depends on the input to the hold pin) p5_5 input port hold input (2) hold input (2) p5_6 input port ale output (?l? is output) ale output (?l? is output) p5_7 input port rdy input rdy input p6, p7, p8, p9, p10 input port input port input port rej09b0392-0064 rev.0.64 oct 12, 2007 page 35 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 5. reset 5.2 brown-out reset the microcomputer resets pins, the cpu, or sfrs by setting the built-in voltage detection 0 circuit. the voltage detection 0 circuit monitors the voltage applied to the vcc1 pin (vdet0). the microcomputer resets pins, the cpu, and sfr as s oon as the voltage that is applied to the vcc1 pin drops to vdet0 or below. then, 125 khz on-chip oscillator clock starts counting when the voltage that is applied to the vcc1 pin goes up to vdet0 or above. the internal reset si gnal becomes ?h? after the 125 khz on-chip oscillator clock is counted 32 times, and then reset sequen ce starts (see figure 5.2). the 125 khz on-chip oscillator clock divided by 8 is automatically selected as a cpu clock after reset. refer to 4. ?special function registers (sfrs)? for the sfr status after brown-out reset. the internal ram is not reset. when the voltage that is applied to the vcc1 pin drops to vdet0 or below while writing data to the internal ram, the internal ram is in an indeterminate state. refer to 6. ?voltage detection circuit? for details of the voltage detection 0 circuit. 5.3 software reset the microcomputer resets pins, the cpu, and sfrs when the pm03 bit in the pm0 register is set to 1 (microcomputer reset). then the microcomputer exec utes the program in an address determined by the reset vector. the 125 khz on-chip oscillator clock di vided by 8 is automatically selected as a cpu clock after reset. in the software reset, the mi crocomputer does not reset a part of the sfrs. refer to 4. ?special func- tion registers (sfrs)? for details. the internal ram is not reset. 5.4 watchdog timer reset the microcomputer resets pins, the cpu, and sfrs when the pm12 bit in the pm1 register is set to 1 (reset when watchdog timer underflows) and the watchdog timer underflows. then the microcomputer executes the program in an address dete rmined by the reset vector. the 125 khz on-chip oscillator clock divided by 8 is automatically selected as a cpu clock after reset. in the watchdog timer reset, th e microcomputer does not reset a part of the sfrs. refer to 4. ?special function registers (sfrs)? for details. the internal ram is not reset. when the watchdog timer underflows while writing data to the internal ram, the internal ram is in an indeterminate state. refer to 13. ?watchdog timer? for details. 5.5 oscillation stop detection reset the microcomputer resets and stops pins, the cpu, an d sfrs when the cm27 bit in the cm2 register is 0 (reset when oscillation stop detected), if it detects main clock oscillation circuit stop. refer to 10.6 ?oscillation stop and re-osc illation detect function? for details. in the oscillation st op detection reset, the microcomputer does not reset a part of the sfrs. refer to 4. ?special function registers (sfrs)? for details. processor mode remains unchanged since bits pm01 to pm00 in the pm0 register are not reset. rej09b0392-0064 rev.0.64 oct 12, 2007 page 36 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 5. reset 5.6 internal space figure 5.3 shows cpu register status after reset. refer to 4. ?special function registers (sfrs)? for sfr states after reset. figure 5.3 cpu register status after reset b15 b0 data register (r0) address register (a0) frame base register (fb) program counter (pc) interrupt table register (intb) user stack pointer (usp) interrupt stack pointer (isp) static base register (sb) flag register (flg) 0000h 0000h 0000h c d z s b o i u ipl 0000h 0000h 0000h 0000h 0000h b19 b0 content of addresses ffffeh to ffffch b15 b0 b15 b0 b15 b0 b7 b8 00000h data register (r1) data register (r2) data register (r3) address register (a1) 0000h 0000h 0000h rej09b0392-0064 rev.0.64 oct 12, 2007 page 37 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 6. voltage detection circuit 6. voltage detection circuit the voltage detection circuit consists of the voltage detection 0 circuit and the low voltage detection circuit. the voltage detection 0 circuit monitors the voltage a pplied to the vcc1 pin. the microcomputer is reset if the voltage detection 0 circuit detects vcc1 is vdet0 or below. the low voltage detection circuit also monitors the vo ltage applied to the vcc1 pin. the low voltage detec- tion signal is generated when the low voltage detect ion circuit detects that vcc1 passes through vdet2. this signal generates the low voltage detection interr upt. the vc13 bit in the vcr1 register determines whether vcc1 is vdet2 a nd above or below vdet2. the voltage detection circuit is available when vcc1 = 5 v. figure 6.1 shows a voltage detection circuit block diagram. figure 6.1 voltage detectio n circuit block diagram + - b3 vc25 + - vdet2 internal reference voltage vc27 vcc1 vc13 bit low voltage detection interrupt signal voltage detection 0 signal vdet0 vcr1 register noise filter voltage detection 0 circuit low voltage detection circuit rej09b0392-0064 rev.0.64 oct 12, 2007 page 38 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 6. voltage detection circuit figure 6.2 registers vcr1 and vcr2 b7 0 0 0 0 0 0 0 b6 b5 b4 b1 b2 b3 voltage detection 2 circuit flag register symbol vcr1 address 0019h bit symbol bit name rw ? (b2-b0) after reset (2) 00001000b rw b0 function reserved bits vc13 ro rw 0 : vcc1 < vdet2 1 : vcc1 vdet2 reserved bits set to 0 low voltage monitor flag (1) ? (b7-b4) notes : 1. the vc13 bit is enabled when the vc27 bit in the vcr2 re gister is set to 1 (low voltage detection circuit enabled). the vc13 bit is always 1 (vcc1 vdet2) when the vc27 bit is set to 0 (low voltage detection circuit disabled). 2. this register dose not change at software reset, watchdog timer reset, and oscillation stop detection reset. set to 0 b7 0 0 0 0 0 b6 b5 b4 b1 b2 b3 voltage detection ci rcuit operation enable register (1) symbol vcr2 address 001ah bit symbol bit name rw after reset (4) 000x0000b (hardware reset 1) 001x0000b (brown-out reset) b0 function rw notes : 1. write to this register after setting the prc3 bit in the prcr register to 1 (write enabled). 2. to use brown-out reset, set the vc25 bit to 1 (voltage detection 0 circuit enabled). 3. when the vc13 bit in the vcr1 register and d42 bit in the d4int register are used or the d40 bit is set to 1 (low voltage detection interrupt enabled), set the vc27 bit to 1 (low voltage detection circuit enabled). 4. this register does not change at software reset, wa tchdog timer reset, and oscillation stop detection reset. 5. the detection circuit does not start operation until td(e -a) elapses after the vc25 bit or vc27 bit is set to 1. vc25 voltage detection 0 enable bit (2, 5) 0 : disable voltage detection 0 circuit 1 : enable voltage detection 0 circuit ? (b3-b0) rw reserved bits set to 0 ? (b4) ? no register bit. if necessary, set to 0. read as undefined value ? (b6) reserved bit set to 0 rw vc27 low voltage monitor bit (3, 5) 0 : disable low voltage detection circuit 1 : enable low voltage detection circuit rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 39 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 6. voltage detection circuit figure 6.3 d4int register b7 b6 b5 b4 b1 b2 b3 low voltage detection interrupt register (1) symbol d4int address 001fh bit symbol bit name rw after reset 00h b0 function notes : 1. write to this register after setting the prc3 bit in the prcr register to 1 (write enabled). 2. this flag is enabled when the vc27 bit in the vcr2 regi ster is set to 1 (low voltage detection circuit enabled). if the vc27 bit is set to 0 (low voltage detection ci rcuit disabled), the d42 bit is set to 0 (not detected). 3. this bit is set to 0 by writing a 0 in a program. (writing a 1 has no effect.) 4. if the low voltage detection interrupt needs to be used to get out of stop mode again after once used for that purpose, reset the d41 bit by writing a 0 and then a 1. 5. the d40 bit is effective when the vc27 bit in the vcr2 register = 1. to set the d40 bit to 1, set bits in the following order. (a) set the vc27 bit to 1. (b) wait for td(e-a) until the detection circuit is actuated. (c) wait for the sampling time. (see table 6.3 sampling period .) (d) set the d40 bit to 1. 6. this bit is used for wait mode exiting control when the cm02 bit in the cm0 register is 1 (stop peripheral function clock f1 in wait mode). d40 rw low voltage detection interrupt enable bit (5) 0 : disabled 1 : enabled rw (3) d42 voltage change detection flag (2) 0 : not detected 1 : vdet2 passing detection d43 wdt overflow detect flag 0 : not detected 1 : detected df0 df1 sampling clock select bit b5 b4 0 0 : d4int clock divided by 8 0 1 : d4int clock divided by 16 1 0 : d4int clock divided by 32 1 1 : d4int clock divided by 64 rw (3) rw rw no register bits. if necessary, set to 0. read as undefined value. ? (b7-b6) ? d41 rw stop mode deactivation control bit (4, 6) 0 : disabled (the low voltage detection interrupt is not used for recovery from stop mode) 1 : enabled (the low voltage detection interrupt is used for recovery from stop mode) rej09b0392-0064 rev.0.64 oct 12, 2007 page 40 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 6. voltage detection circuit figure 6.4 vw0c register b7 1 0 1 b6 b5 b4 b1 b2 b3 voltage monitor 0 circui t control register (1) symbol vw0c address 002ah bit symbol bit name rw after reset (2) 10001x10b (hardware reset 1) 11001x11b (brown-out reset) b0 function rw 1. set the prc3 bit in the prcr register to 1 (write enabled) to rewrite the vw0c register. 2. the value of this register remain unchanged after software reset, watchdog timer reset, or oscillation stop detection reset. 3. set the vc25 bit in the vcr2 register to 1 (voltage detection 0 circuit enabled) to enable the vw0c0 bit. set the vw0c0 bit to 0 (disabled) when the vc25 bit is set to 0 (voltage detection 0 circuit disabled). ? (b2) reserved bit set to 0. read as undefined value ? (b3) reserved bit read as undefined value vw0f0 vw0f1 reserved bits set to 1 sampling clock select bit b5 b4 0 0 : foco-s divided by 1 0 1 : foco-s divided by 2 1 0 : foco-s divided by 4 1 1 : foco-s divided by 8 ? (b7-b6) ro rw rw vw0c0 rw brown-out reset enable bit (3) 0 : disabled 1 : enabled vw0c1 rw voltage monitor 0 digital filter disable mode select bit 0 : enable digital filter 1 : disable digital filter notes : rej09b0392-0064 rev.0.64 oct 12, 2007 page 41 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 6. voltage detection circuit 6.1 brown-out reset figure 6.5 is a block diagram illustra ting brown-out reset gener ation circuit. table 6.1 shows a setting pro- cedure of the bits for brown-out reset. figure 6.6 provides an example of brown-out reset operation. when using brown-out resetbrown-out reset to exit st op mode, set the vw0c1 bit in the vw0c register to 1 (digital filter disabled). figure 6.5 brown-out reset generation circuit table 6.1 setting procedures of the bits for brown-out reset procedure when using the digital filter when not using the digital filter 1 set the vc25 bit in the vcr2 register to 1 (voltage detection 0 circuit enabled) 2 wait for td (e-a) 3 use bits vw0f0 to vw0f1 in the vw0c regis- ter to select the digital filter sampling clock. set the vw0c1 bit to 0 (digital filter enabled), bits 6 and 7 to 1 set the vw0c1 bit in the vw0c register to 1 (digital filter disabled), and bits 6 and 7 to 1 4 set bit 2 in the vw0c register to 0 (setting bit 2 to 0 once again after procedure 3 is neces- sary) 5 set the cm14 bit in the cm1 register to 0 (125 khz on-chip oscillator oscillates) - 6 wait for digital filter sampling clock x 4 cycles - (no wait time) 7 set the vw0c0 bit in the vw0c register to 1 (brown-out reset enabled) + - 1/2 1/2 1/2 voltage detection 0 circuit vc25 vcc1 internal reference voltage when the vc25 bit is set to 0 (disabled), the voltage detection 0 signal becomes ?h.? voltage detection 0 signal foco-s vw0f1 to vw0f0 = 00b = 01b = 10b = 11b 1 1 brown-out reset generation circuit vw0c0 to vw0c1, vw0f0 to vw0f1 = the bits in the vw0c register vc25 = the bit in the vc2 register vw0c0 vw0c1 brown-out reset signal digital filter vw0c1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 42 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 6. voltage detection circuit figure 6.6 brown-out reset operation example 6.2 low voltage detection interrupt if the d40 bit in the d4int register is set to 1 (low voltage detection interrupt enabled), the low voltage detection interrupt request is generated when the voltage applied to the vcc1 pin is above or below vdet2. the low voltage detection interrupt shares the same interrupt vector with the watchdog timer inter- rupt, oscillation stop, and re-o scillation detect ion interrupt. set the d41 bit in the d4int register to 1 (enabled) to use the low voltage detection interrupt to exit stop mode. the d42 bit in the d4int register is set to 1 as soon as the voltage applied to the vcc1 pin reaches vdet2 due to the voltage rise and voltage drop. when the d42 bit changes 0 to 1, the low voltage detec- tion interrupt request is generated. set the d42 bit to 0 by program. however, when the d41 bit is set to 1 and the microcomputer is in stop mode, the low voltage detection interrupt request is generated regard- less of the d42 bit state if the voltage applied to th e vcc1 pin is detected to be above vdet2. the micro- computer then exits stop mode. table 6.2 shows low voltage detection interrupt request generation conditions. bits df1 to df0 in the d4int register determine t he sampling period that detects the voltage applied to the vcc1 pin reaches vdet2. table 6.3 shows the sampling periods. vdet0 internal reset signal vcc the above diagram shows an instance in which the following conditions are all met. ? the vc25 bit in the vcr2 register = 1 (voltage detection 0 circuit enabled) ? the vw0c0 bit in the vw0c register = 1 (brown-out reset enabled) pins, the cpu, and sfrs are initialized when the internal reset signal becomes low. the microcomputer executes the program in an address indicated by the reset vector when the internal reset signal changes low to high. refer to 4. sfrs for the sfr status after reset. 1 foco-s 32 digital filter sampling clock 4 cycles when the vw0c1 bit is 0 (digital filter enabled) internal reset signal when the vw0c1 bit is 1 (digital filter disabled) 1 foco-s 32 vw0c1 = the bit in the vw0c register rej09b0392-0064 rev.0.64 oct 12, 2007 page 43 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 6. voltage detection circuit - indicates either 0 or 1 is settable. note: 1. the status except wait mode and stop mo de is handled as normal mode. (refer to 10. ?clock gen- eration circuit? ) 2. refer to 6.3 ?limitations on exiting stop mode? and 6.4 ?limitations on exiting wait mode? . 3. an interrupt request for voltage reduction is gene rated after the value of the vc13 bit changes and a sampling time elapses. see figure 6.8 ?low voltage detection interrupt generation circuit operation example? for details. figure 6.7 low voltage detection interrupt generation block diagram table 6.2 low voltage detection in terrupt request generation conditions operating mode vc27 bit d40 bit d41 bit d42 bit cm02 bit vc13 bit normal operating mode (1) 11 - 0 to 1 - 0 to 1 (3) 1 to 0 (3) wait mode (2) - 0 to 1 0 0 to 1 (3) 1 to 0 (3) - 1 0 to 1 stop mode (2) 1 - 0 0 to 1 table 6.3 sampling periods cpu clock (d4int clock) (mhz) sampling clock ( s) df1 to df0 = 00 (cpu clock divided by 8) df1 to df0 = 01 (cpu clock divided by 16) df1 to df0 = 10 (cpu clock divided by 32) df1 to df0 = 11 (cpu clock divided by 64) 16 3.0 6.0 12.0 24.0 low voltage detection interrupt generation circuit watchdog timer interrupt signal the d42 bit is set to 0 (not detected) by program. when the vc27 bit is set to 0 (low voltage detection circuit disabled), the d42 bit is set to 0. vc27 vc13 low voltage detection circuit d4int clock (the clock with which it operates also in wait mode) d42 df1, df0 1/2 00b 01b 10b 11b 1/2 1/2 1/8 non-maskable interrupt sognal oscillation stop, re-oscillation detection interrupt signal low voltage detection interrupt signal watchdog timer block this bit is set to 0 (not detected) by program. watchdog timer underflow signal d43 d41 cm02 wait instruction (wait mode) d40 vcc1 vref + - noise rejection (rejection range : 200 ns) low voltage detection signal the low voltage detection signal becomes h when the vc27 bit is set to 0 (disabled). noise rejection circuit digital filter cm10 rej09b0392-0064 rev.0.64 oct 12, 2007 page 44 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 6. voltage detection circuit figure 6.8 low voltage detection interrupt generation circuit operation example 6.3 limitations on exiting stop mode the low voltage detection interrupt is immediatel y generated and the microcomputer exits stop mode if the cm10 bit in the cm1 register is set to 1 (stop mode) under the conditions below. ? the vc27 bit in the vcr2 register is set to 1 (low voltage detection circuit enabled) ? the d40 bit in the d4int register is set to 1 (low voltage detection interrupt enabled) ? the d41 bit in the d4int register is set to 1 (low voltage detection interrupt is used to exit stop mode) ? the voltage applied to the vcc1 pin is higher than vdet2 (the vc13 bit in the vcr1 register is 1) if the microcomputer is set to enter stop mode when the voltage applied to the vcc1 pin drops below vdet2 and to exit stop mode when the voltage applied rises to vdet2 or above, set the cm10 bit to 1 when vc13 bit is 0 (vcc1 < vdet2). 6.4 limitations on exiting wait mode the low voltage detection interrupt is immediately generated and the microcomputer exits wait mode if wait instruction is executed under the conditions below. ? the cm02 bit in the cm0 register is set to 1 (stop peripheral function clock) ? the vc27 bit in the vcr2 register is set to 1 (low voltage detection circuit enabled) ? the d40 bit in the d4int register is set to 1 (low voltage detection interrupt enabled) ? the d41 bit in the d4int register is set to 1 (low voltage detection interrupt is used to exit wait mode) ? the voltage applied to the vcc1 pin is higher than vdet2 (the vc13 bit in the vcr1 register is 1) if the microcomputer is set to enter wait mode w hen the voltage applied to the vcc1 pin drops below vdet2 and to exit wait mode when the voltage applie d rises to vdet2 or above, perform wait instruc- tion when the vc13 bit is 0 (vcc1 < vdet2). output of the digital filter (2) d42 bit notes : 1. the d40 bit is set to 1 (low voltage detection interrupt enabled). 2. output of the digital filter is shown in figure 6.7. low voltage detection interrupt signal no low voltage detection interrupt signals are generated when the d42 bit is ?h.? sampling sampling sampling sampling set the d42 bit to 0 (not detected) by program. vc13 bit vcc1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 45 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 6. voltage detection circuit 6.5 cold start-up / warm start-up discrimination as for the cold start-up / warm start-up discriminat ion, the cwr bit in the rstfr register determines either cold start-up (reset process) when power-on or warm start-up (reset process) when reset signal is applied during the microcomputer running. the value of the cwr bit is 0 when power is applied. the cwr bit is also set to 0 after brown-out reset. the cwr bit is set to 1 by writing a 1 in a program and does not change at hardware reset 1, software reset, watchdog timer reset, and oscillation stop detect ion reset. use brown-out reset for cold start-up / warm start-up discrimination. follow table 6.1 setting procedures of the bits for brown-out reset to set the bits for brown-out reset. figure 6.9 shows cold start-up / warm start-up discrimination example. figure 6.10 shows rstfr reg- ister. figure 6.9 cold start-up / warm start-up discrimination example set to 1 by program 5v vdet0 cwr bit brown-out reset vcc1 set to 1 by program 0v the above diagram shows an instance in which the digital filter is not used. rej09b0392-0064 rev.0.64 oct 12, 2007 page 46 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 6. voltage detection circuit figure 6.10 rstfr register b7 0 0 b6 b5 b4 b1 b2 b3 reset source determine flag symbol rstfr address 0018h bit symbol bit name rw cwr after reset 0xxxxxxxb (1) rw b0 function cold start-up / warm start determine flag (2, 3) ? (b5-b1) ro rw read as undefined value reserved bits set to 0 reserved bits ? (b7-b6) 1. the cwr bit is set to 0 (cold start-up) after power acti vation or brown-out reset. the cwr bit remains unchanged after hardware reset 1, software reset, watchdog timer reset, or oscillation stop detection reset. 2. the cwr bit is set to 1 by writing a 1 in a program (writing a 0 has no effect). 3. the cwr bit is undefined when the vw0c0 bit in the vw 0c register is set to 0 (brown-out reset disabled). 0 : cold start-up 1 : warm start-up notes : rej09b0392-0064 rev.0.64 oct 12, 2007 page 47 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 7. processor mode 7. processor mode 7.1 types of processor mode three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode. table 7.1 show s the features of processor modes. note: 1. refer to 8. ?bus? for details. 7.2 setting processor modes processor mode is set by usin g the cnvss pin and bits pm01 to pm00 in the pm0 register. table 7.2 shows the processor mode after hardware reset. table 7.3 shows bits pm01 to pm00 set values and processor modes notes: 1. if the microcomputer is reset in hardware by applying vcc1 to the cnvss pin (hardware reset 1 or brown-out reset), the internal rom cannot be acce ssed regardless of the status of bits pm10 to pm00. 2. the multiplexed bus cannot be assigned to the entire cs space. rewriting bits pm01 to pm00 places the microcomputer in the corresponding processor mode regardless of whether the input level on the cn vss pin is ?h? or ?l?. no te, however, that bits pm01 to pm00 cannot be rewritten to 01b (memory expansion mode) or 11b (microprocessor mode) at the same time bits pm07 to pm02 are rewritten. note also that these bits cann ot be rewritten to enter microprocessor mode in the internal rom, nor can they be rewritten to exit microprocessor mode in areas overlapping the internal rom. if the microcomputer is reset in hardware by appl ying vcc1 to the cnvss pin (hardware reset 1 or brown-out reset), the internal rom cannot be accessed regardless of bits pm01 to pm00. figures 7.1 to 7.3 show the pm0 register and pm1 re gister. figure 7.4 show the memory map in single- chip mode. table 7.1 features of processor modes processor modes access space pins which are assigned i/o ports single-chip mode sfr, internal ram, internal rom all pins are i/o ports or peripheral function i/ o pins memory expansion mode sfr, internal ram, internal rom, external area (1) some pins serve as bus control pins (1) microprocessor mode sfr, internal ram, external area (1) some pins serve as bus control pins (1) table 7.2 processor mode after hardware reset cnvss pin input leve l processor modes vss single-chip mode vcc1 (1, 2) microprocessor mode table 7.3 bits pm01 to pm00 set values and processor modes bits pm01 to pm 00 processor modes 00b single-chip mode 01b memory expansion mode 10b do not set 11b microprocessor mode rej09b0392-0064 rev.0.64 oct 12, 2007 page 48 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 7. processor mode figure 7.1 pm0 register b7 b6 b5 b4 b1 b2 b3 processor mode register 0 (1) symbol pm0 address 0004h bit symbol bit name rw pm00 after reset (4) 00000000b (cnvss pin = ?l?) 00000011b (cnvss pin = ?h?) rw 1. write to this register after setting the prc1 bit in the prcr register to 1 (write enabled). 2. bits pm02, and pm04 to pm07 are effective when bits pm01 and pm00 are set to 01b (memory expansion mode) or 11b (microprocessor mode). 3. to set bits pm01 and pm00 to 01b and bits pm05 and pm04 to 11b (multiplexed bus assigned to the entire cs space), apply an ?h? signal to the byte pin (external data bus is 8 bits wide). while the cnvss pin is held ?h? (= vcc1), do not rewrite the pm05 and pm04 bits to 11b after reset. if bits pm05 and pm04 are set to 11b during memory expansion mode, p3_1 to p3_7 and p4_0 to p4_3 become i/o ports, in wh ich case the accessible area for each cs is 256 bytes. 4. bits pm01 and pm00 do not change at software reset, wa tchdog timer reset, and oscillation stop detection reset. b0 function b1 b0 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : do not set 1 1 : microprocessor mode processor mode bit (4) pm01 pm02 r/w mode select bit (2) 0 : rd, bhe, wr 1 : rd, wrh, wrl pm03 software reset bit setting this bit to 1 resets the microcomputer. read as 0 rw rw rw bclk output disable bit (2) pm07 0 : bclk is output 1 : bclk is not output (pin is left high-impedance) rw pm06 port p4_0 to p4_3 function select bit (2) 0 : address output 1 : port function (address is not output) rw pm04 multiplexed bus space select bit (2) b5 b4 0 0 : multiplexed bus is unused (separate bus in the entire cs space) 0 1 : allocated to cs2 space 1 0 : allocated to cs1 space 1 1 : allocated to the entire cs space (3) pm05 rw rw notes : rej09b0392-0064 rev.0.64 oct 12, 2007 page 49 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 7. processor mode figure 7.2 pm1 register b7 0 b6 b5 b4 b1 b2 b3 processor mode register 1 (1) symbol pm1 address 0005h bit symbol bit name rw pm10 after reset 00001000b rw 1. write to this register after setting the prc1 bit in the prcr register to 1 (write enabled). 2. bits pm10 and pm13 are automatically set to 1 while the fmr01 bit in the fmr0 register is set to 1 (cpu rewrite mode). 3. bits pm11, pm14, and pm 15 are effective when bits pm01 and pm00 are set to 01b (memory expansion mode) or 11b (microprocessor mode). 4. the pm12 bit is set to 1 by writing a 1 in a program (writing a 0 has no effect). the pm12 bit is automatically set to 1 when the cspro bit in the cspr regist er is 1 (count source protection mode enabled). 5. when the pm17 bit is set to 1 (wait state), one wait state is inserted when accessing the internal ram or internal rom. when the pm17 bit is set to 1 and accesses an external area, set the csiw bit in the csr register (i = 0 to 3) to 0 (wait state). 6. the access area is changed by the pm 13 bit as listed in the table below. b0 function 0 : cs2 (0e000h to 0ffffh ) 1 : data flash (0e000h to 0ffffh) cs2 area switch bit (data flash enable bit) (2) pm11 pm12 pm13 wait bit (5) pm17 0 : no wait state 1 : wait state (1 wait) rw rw memory area expansion bit (3) b5 b4 0 0 : 1-mbyte mode (no expansion) 0 1 : do not set 1 0 : do not set 1 1 : 4-mbyte mode rw rw 0 : address output 1 : port function port p3_7 to p3_4 function select bit (3) internal reserved area expansion bit (2, 6) (note 6) rw watchdog timer function select bit (4) 0 : watchdog timer interrupt 1 : watchdog timer reset rw pm14 pm15 internal access area external program rom 1 ram reserved bit set to 0 rw ? (b6) pm13 = 1 address 04000h to 0cfffh are reserved address 80000h to cffffh are reserved (in memory expansion mode) the entire area is usable the entire area is usable pm13 = 0 address 04000h to 0cfffh are usable address 80000h to cffffh are usable note that 08000h to 0cfffh are reserved when pm10 is set to 1 during microprocessor mode. up to addresses d0000h to fffffh (192 kbytes) up to addresses 00400h to 03fffh (15 kbytes) notes : rej09b0392-0064 rev.0.64 oct 12, 2007 page 50 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 7. processor mode figure 7.3 prg2c register b7 0 b6 b5 b4 b1 b2 b3 program 2 area control register (1) symbol prg2c (1) address 0010h bit symbol bit name rw prg2c after reset xxxxxxx0h rw b0 function ? (b7-b2) ? no register bits. if necessary, set to 0. read as undefined value 0 : enable program rom 2 1 : disable program rom 2 set to 0 rw ? (b1) program rom 2 disable bit reserved bit note : 1. write to this register after setting the prc6 bit in the prcr register to 1 (write enabled). rej09b0392-0064 rev.0.64 oct 12, 2007 page 51 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 7. processor mode 7.3 internal memory the internal ram can be used in all processor modes. the range of the internal ram depends on the set- ting of the pm 13 bit in the pm1 register. the internal rom is used in single-chip mode and me mory expansion mode. three internal roms are available: data flash, program rom 2, and program rom 1. data flash includes block a (addresses 0e000h to 0efffh) and block b (addresses 0f000h to 0ffffh). when data flash is selected by the setting of the pm10 bit in the pm 1 register, both block a and block b can be used. table 7.4 shows data flash (addresses 0e000h to 0ffffh). set the prg2c0 bit in the prg2c register to select program rom 2. table 7.5 shows program rom 2 (addresses 10000h to 13fffh). do not use the last 16 bytes (addresses 13ff0h to 13fffh) when using program rom 2 in single-chip mode or memory expansion mode. these bytes are assigned as the user boot code area (refer to 22.1.2 ?user boot function? ). the range of program rom 1 depends on the setting of the pm13 bit in the pm1 register. figure 7.4 indi- cates the memory map in single-chip mode. table 7.4 data flash (addresses 0e000h to 0ffffh) pm10 bit in pm1 register 0 1 processor modes single-chip mode unusable data flash memory expansion mode external area data flash microprocessor mode external area reserved area table 7.5 program rom 2 (addresses 10000h to 13fffh) prg2c0 bit in prg2c register 0 1 processor modes single-chip mode program rom 2 unusable memory expansion mode program rom 2 external area microprocessor mode reserved area external area rej09b0392-0064 rev.0.64 oct 12, 2007 page 52 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 7. processor mode figure 7.4 memory map in single-chip mode single-chip mode sfr internal ram unusable internal rom (program rom 1) 00000h 00400h xxxxxh yyyyyh fffffh sfr 0d000h 0d800h 0e000h 10000h 14000h unusable unusable internal rom (3) (program rom 2) internal rom (2) (data flash) notes : 1. if the pm13 bit is set to 0, 15 kbytes of the internal ram and 192 kbytes of the internal rom can be used. 2. data flash can be used when the pm10 bit in the pm1 register is 1 (0e000h to 0ffffh = data flash). 3. program rom 2 can be used when the prg2c0 bit in the prg2c register is 0 (program rom 2 enabled). size address yyyyyh 128 kbytes e0000h 256 kbytes d0000h (1) size address xxxxxh 12 kbytes 033ffh 16 kbytes 512 kbytes internal ram internal rom 31 kbytes pm13 = 0 03fffh (1) 03fffh (1) d0000h (1) size address yyyyyh 128 kbytes e0000h 256 kbytes c0000h size address xxxxxh 12 kbytes 033ffh 16 kbytes 043ffh 512 kbytes 80000h internal ram internal rom 31 kbytes 07fffh pm13 = 1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 53 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus 8. bus during memory expansion or microprocessor mode, so me pins serve as the bus control pins to perform data input /output to and from external devices. these bus control pins include a0 to a19, d0 to d15, cs0 to cs3 , rd, wrl / wr , wrh / bhe , ale, rdy , hold , hlda , and bclk. 8.1 bus mode bus mode, either multiplexed or separate, can be selected using bits pm05 and pm04 in the pm0 regis- ter. table 8.1 shows the difference between separate bus and multiplexed bus. 8.1.1 separate bus in this bus mode, data and address are separate. 8.1.2 multiplexed bus in this bus mode, data and address are multiplexed. 8.1.2.1 when the input l evel on byte pin is hi gh (8-bit data bus) d0 to d7 and a0 to a7 are multiplexed. 8.1.2.2 when the input level on byte pin is low (16-bit data bus) d0 to d7 and a1 to a8 are multiplexed. d8 to d1 5 are not multiplexed. do not use d8 to d15. exter- nal devices connecting to a multiplexed bus are a llocated to only the even addresses of the micro- computer. odd addresses cannot be accessed. notes: 1. see table 8.6 ?pin functions for each processor mode? for bus control signals other than the above. 2. it changes with a setting of pm05 and pm04, and area to access. see table 8.6 ?pin functions for each processor mode? for details. table 8.1 difference between separate bus and multiplexed bus pin name (1) separate bus multiplexed bus byte = ?h? byte = ?l? p0_0 to p0_7 / d0 to d7 d0 to d7 (note 2) (note 2) p1_0 to p1_7 / d8 to d15 d8 to d15 i/o port p1_0 to p1_7 (note 2) p2_0 / a0 (/ d0 / -) a0 a0 d0 a0 p2_1 to p2_7 / a1 to a7 (/ d1 to d7 / d0 to d6) a1 to a7 a1 to a7 d1 to d7 a1 to a7 d0 to d6 p3_0 / a8 (/ - / d7) a8 a8 a8 d7 rej09b0392-0064 rev.0.64 oct 12, 2007 page 54 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus 8.2 bus control the following describes the signals needed for accessin g external devices and the functionality of soft- ware wait. 8.2.1 address bus the address bus consists of 20 lines: a0 to a19. the address bus width can be chosen to be 12, 16, or 20 bits by using the pm06 bit in the pm0 register and the pm11 bit in the pm1 register. table 8.2 shows the set value of bits pm06 and pm11, and address bus width. note: 1. no values other than th ose shown above can be set. when processor mode is changed from single-chip mode to memory expansion mode, the address bus is indeterminate until any external area is accessed. 8.2.2 data bus when input on the byte pin is high (data bus is 8 bi ts wide), 8 lines d0 to d7 comprise the data bus; when input on the byte pin is low (data bus is 16 bits wide), 16 lines d0 to d15 comprise the data bus. do not change the input level on the byte pin while in operation. 8.2.3 chip select signal the chip select (hereafter referred to as the cs ) signals are output from the csi (i = 0 to 3) pins. these pins can be chosen to func tion as i/o ports or as cs by using the csi bit in the csr register. figure 8.1 shows the csr register. during 1-mbyte mode, the external area can be separated into up to 4 by the csi signal which is output from the csi pin. during 4-mbyte mode, csi signal or bank number is output from the csi pin. refer to 9. ?memory space expansion function? . figure 8.2 shows examples of address bus and csi sig- nal output in 1-mbyte mode. table 8.2 set value of bits pm06 and pm11, and address bus width bits set value (1) pin function address bus width pm11 = 1 p3_4 to p3_7 12 bits pm06 = 1 p4_0 to p4_3 pm11 = 0 a12 to a15 16 bits pm06 = 1 p4_0 to p4_3 pm11 = 0 a12 to a15 20 bits pm06 = 0 a16 to a19 rej09b0392-0064 rev.0.64 oct 12, 2007 page 55 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus figure 8.1 csr register b7 b6 b5 b4 b1 b2 b3 chip select control register symbol csr address 0008h bit symbol bit name rw after reset 01h 1. when the rdy signal is used in the area indicated by csi (i = 0 to 3) or the multiplex bus is used, set the csiw bit to 0 (wait state). 2. when the pm17 bit in the pm1 register is set to 1 (wait state), set the csiw bit to 0 (wait state). 3. when the csiw bit = 0 (wait state), the number of wait states can be selected using bits csei1w to csei0w in the cse register. b0 function cs0 rw 0 : disable chip select output (functions as i/o port) 1 : enable chip select output cs0 output enable bit cs1 rw cs1 output enable bit cs2 rw cs2 output enable bit cs3 rw cs3 output enable bit cs0w rw 0 : wait state 1 : no wait state (1, 2, 3) cs0 wait bit cs1w rw cs1 wait bit cs2w rw cs2 wait bit cs3w rw cs3 wait bit notes : rej09b0392-0064 rev.0.64 oct 12, 2007 page 56 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus figure 8.2 examples of address bus and csi signal output in 1-mbyte mode example 1 to access the external area indicated by csj in the next cycle after accessing the external area indicated by csi the address bus and chip select signal both change state between these two cycles. note : 1. these examples show the address bus and chip select si gnal when accessing areas in two successive cycles. the chip select bus cycle may be extended more than two cycles depending on a combination of these examples. bclk read signal data bus address bus csi access to the external area indicated by csi access to the external area indicated by csj address data csj data example 2 to access the internal rom or internal ram in the next cycle after accessing the external area indicated by csi the chip select signal changes state but the address bus does not change state bclk read signal data bus address bus csi access to the external area indicated by csi access to the internal rom or internal ram address data example 3 to access the external area indicated by csi in the next cycle after accessing the external area indicated by the same csi the address bus changes state but the chip select signal does not change state bclk read signal data bus address bus csi access to the external area indicated by csi access to the same external area address data data example 4 not to access any area (nor instruction prefetch generated) in the next cycle after accessing the external area indicated by csi neither the address bus nor the chip select signal changes state between these two cycles bclk read signal data bus address bus csi access to the external area indicated by csi no access address data address address shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3 (not including i, however) rej09b0392-0064 rev.0.64 oct 12, 2007 page 57 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus 8.2.4 read and write signals when the data bus is 16 bits wide, the read and wr ite signals can be chosen to be a combination of rd , bhe , and, wr or a combination of rd , wrl , and wrh by using the pm02 bit in the pm0 register. when the data bus is 8 bits wide, use a combination of rd , wr , and bhe . table 8.3 shows the operation of rd , wrl , and wrh signals. table 8.4 shows the operation of rd , wr , and bhe signals. note: 1. do not use. 8.2.5 ale signal the ale signal latches the address when accessing the multiplexed bus space. latch the address when the ale signal falls. figure 8.3 ale signal, address bus, data bus table 8.3 operation of rd , wrl , and wrh signals data bus width rd wrl wrh status of external data bus 16-bit (byte pin input = ?l?) l h h read data h l h write 1 byte of data to an even address h h l write 1 byte of data to an odd address h l l write data to both even and odd addresses table 8.4 operation of rd , wr , and bhe signals data bus width rd wr bhe a0 status of external data bus 16-bit (byte pin input = ?l?) h l l h write 1 byte of data to an odd address l h l h read 1 byte of data from an odd address h l h l write 1 byte of data to an even address l h h l read 1 byte of data from an even address h l l l write data to both even and odd addresses l h l l read data from both even and odd addresses 8-bit (byte pin input = ?h?) hl ? (1) h or l write 1 byte of data lh ? (1) h or l read 1 byte of data when byte pin input = ?h? when byte pin input = ?l? ale address data address (1) a0/d0 to a7/d7 a8 to a19 ale address data address a1/d0 to a8/d7 a9 to a19 address a0 note : 1. if the entire cs space is assigned a multip lexed bus, these pins function as i/o ports. rej09b0392-0064 rev.0.64 oct 12, 2007 page 58 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus 8.2.6 rdy signal this signal is provided for accessing external devices which need to be accessed at low speed. if input on the rdy pin is low at the last falling edg e of bclk of the bus cycle, one wait state is inserted in the bus cycle. while in a wait state, the following signals retain the state in which they were when the rdy signal was acknowledged. a0 to a19, d0 to d15, cs0 to cs3 , rd , wrl , wrh , wr , bhe , ale, hlda then, when the input on the rdy pin is detected high at the falling edge of bclk, the remaining bus cycle is executed. figure 8.4 shows examples in wh ich the wait state was inserted into read cycle by rdy signal. to use the rdy signal, set the corresponding bit (bits cs3w to cs0w) in the csr regis- ter to 0 (with wait state). when not using the rdy signal, the rdy pin need to be pulled-up. figure 8.4 examples in which wait state was inserted into read cycle by rdy signal bclk rd csi (i = 0 to 3) rdy tsu (rdy-bclk) bclk rd csi (i = 0 to 3) rdy tsu (rdy-bclk) in an instance of separate bus in an instance of multiplexed bus accept timing of rdy signal accept timing of rdy signal tsu (rdy - bclk) : wait using software : wait using rdy signal : duration for rdy input setup shown above is the case where bits csei1w to csei0w (i = 0 to 3) in the cse register are 00b (one wait state). rej09b0392-0064 rev.0.64 oct 12, 2007 page 59 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus 8.2.7 hold signal this signal is used to transfer control of the bus fr om the cpu or dmac to an external circuit. when the input on the hold pin is pulled low, the microcomputer is placed in a hold state after the bus access at that time finishes. the microcomputer remains in the hold state while the hold pin is held low, during which time the hlda pin outputs a low-level signal. table 8.5 shows the microcompu ter status in hold state. bus-using priorities are given to hold , dmac, and cpu in descending order. however, if the cpu is accessing an odd address in word units, the dmac cannot gain control of the bus during two separate accesses. figure 8.5 bus-using priorities notes: 1. when i/o port function is selected. 2. the watchdog timer does not stop when the cspro bi t in the cspr register is set to 1 (count source protection mode enabled). 8.2.8 bclk output if the pm07 bit in the pm0 register is set to 0 (out put enabled), a clock with the same frequency as that of the cpu clock is output as bclk from the bclk pin. refer to 10.2 ?cpu clock and peripheral function clock? . table 8.5 microcomputer status in hold state item status bclk output a0 to a19, d0 to d15, cs0 to cs3 , rd , wrl , wrh , wr , bhe high-impedance i/o ports p0, p1, p3, p4 (1) high-impedance p6 to p10 maintains status when hold signal is received hlda output ?l? internal peripheral circuits on (but watchdog timer stops) (2) ale undefined hold > dmac > cpu rej09b0392-0064 rev.0.64 oct 12, 2007 page 60 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus notes: 1. when bits pm01 and pm00 are set to 01b (memory expansion mode) and bits pm05 and pm04 are set to 11b (multiplexed bus assigned to the entire cs space), apply ?h? to the byte pin (external data bus 8 bits wide). while the cnvss pin is hel d ?h? (= vcc1), do not rewrite bits pm05 and pm04 to 11b after reset. if bits pm05 and pm04 are set to 11b during memory expansion mode, p3_1 to p3_7 and p4_0 to p4_3 become i/o ports, in which case the accessible area for each cs is 256 bytes. 2. in separate bus mode, these pins serve as the address bus. 3. if the data bus is 8 bits wide, make sure the pm02 bit is set to 0 ( rd , bhe , wr ). 4. when accessing the area that uses a multiplexed bus, these pins output an indeterminate value dur- ing a write. table 8.6 pin functions for each processor mode processor mode memory expansion mode or microprocessor mode memory expansion mode bits pm05 and pm04 00b (separate bus) 01b ( cs2 is for multiplexed bus and the others are for separate bus) 10b ( cs1 is for multiplexed bus and the others are for separate bus) 11b (multi- plexed bus for the entire space) (1) data bus width byte pin 8 bits ?h? 16 bits ?l? 8 bits ?h? 16 bits ?l? 8 bits ?h? p0_0 to p0_7 d0 to d7 d0 to d7 d0 to d7 (4) d0 to d7 (4) i/o ports p1_0 to p1_7 i/o ports d8 to d15 i/o ports d8 to d15 (4) i/o ports p2_0 a0 a0 a0/d0 (2) a0 a0/d0 p2_1 to p2_7 a1 to a7 a1 to a7 a1 to a7 /d1 to d7 (2) a1 to a7 /d0 to d6 (2) a1 to a7 /d1 to d7 p3_0 a8 a8 a8 a8/d7 (2) a8 p3_1 to p3_3 a9 to a11 i/o ports p3_4 to p3_7 pm11 = 0 a12 to a15 i/o ports pm11 = 1 i/o ports p4_0 to p4_3 pm06 = 0 a16 to a19 i/o ports pm06 = 1 i/o ports p4_4 cs0 = 0 i/o ports cs0 = 1 cs0 p4_5 cs1 = 0 i/o ports cs1 = 1 cs1 p4_6 cs2 = 0 i/o ports cs2 = 1 cs2 p4_7 cs3 = 0 i/o ports cs3 = 1 cs3 p5_0 pm02 = 0 wr pm02 = 1 - (3) wrl ? (3) wrl ? (3) p5_1 pm02 = 0 bhe pm02 = 1 ? (3) wrh ? (3) wrh ? (3) p5_2 rd p5_3 bclk p5_4 hlda p5_5 hold p5_6 ale p5_7 rdy i/o ports : function as i/o ports or peripheral function i/o pins. rej09b0392-0064 rev.0.64 oct 12, 2007 page 61 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus 8.2.9 external bus status when internal area is accessed table 8.7 shows the external bus status when internal area accessed. 8.2.10 software wait the pm17 bit in the pm1 register, which is a software -wait-related bit, has an influence over the internal memory and the external area. the sfr area is accessed in 2 bclk or 3 bclk cycles as determined by the pm20 bit in the pm2 reg- ister. data flash, one of the internal roms, is af fected by the pm17 bit and the fmr17 bit in the fmr1 register. see table 8.8 ?bits and bus cycles related to software wait (sfr, internal memory)? for details. software waits can be inserted to the external area by setting the pm17 bit or setting the csiw bit in the csr register or bits csei1w to csei0w in the cs e register for each csi (i = 0 to 3). to use the rdy signal, set the corresponding csiw bit to 0 (with wait state). refer to table 8.9 ?bits and bus cycles related to software wait (external area)? for details. table 8.8 shows the bits and bus cycles related to software wait (sfr, internal memory), figure 8.6 shows the cse register, and table 8.9 shows the bits and bus cycles related to software wait (exter- nal area). notes: 1. the pm 20 bit is valid when the plc07 bit in the plc0 register is set to 1 (pll operation). 2. when 2.7 v vcc1 3.0 v and f (bclk) 16 mhz, or when 3.0 v < vcc1 5.5 v and f (bclk) 20 mhz, 1 wait is necessary to read data flash. use the pm17 bit or the fmr 17 bit to set 1 wait. 3. status after reset. table 8.7 external bus status when internal area accessed item sfr accessed internal rom, ram accessed a0 to a19 address output maintain the last accessed address of external area or sfr d0 to d15 when read high-impedance high-impedance when write output data undefined rd , wr , wrl , wrh rd , wr , wrl , wrh output output ?h? bhe bhe output maintain the last accessed status of exter- nal area or sfr cs0 to cs3 output ?h? output ?h? ale output ?l? output ?l? table 8.8 bits and bus cycles related to software wait (sfr, internal memory) area setting of software-w ait-related bits soft- ware wait bus cycle pm2 register pm20 bit (1) fmr1 register fmr17 bit pm1 register pm17 bit sfr 1--1 wait 2 bclk cycles (3) 0 - - 2 waits 3 bclk cycles internal ram -- 0 no wait 1 bclk cycle (3) 1 1 wait 2 bclk cycles internal rom program rom 1 program rom 2 -- 0 no wait 1 bclk cycle (3) 1 1 wait 2 bclk cycles data flash (2) -0 - 1 wait 2 bclk cycles (3) 1 0 no wait 1 bclk cycle 1 1 wait 2 bclk cycle ? indicates that either 0 or 1 can be set. rej09b0392-0064 rev.0.64 oct 12, 2007 page 62 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus figure 8.6 cse register b7 b6 b5 b4 b1 b2 b3 chip select expansion control register symbol cse address 001bh bit symbol bit name rw after reset 00h 1. set the csiw bit (i = 0 to 3) in the csr register to 0 (wait state) before writing to bits csei1w to csei0w. if the csiw bit needs to be set to 1 (no wait state), set bits csei1w and csei0w to 00b before setting it. b0 function b1 b0 0 0 : 1 wait 0 1 : 2 waits 1 0 : 3 waits 1 1 : do not set cs0 wait expansion bit (1) b3 b2 0 0 : 1 wait 0 1 : 2 waits 1 0 : 3 waits 1 1 : do not set cs1 wait expansion bit (1) b5 b4 0 0 : 1 wait 0 1 : 2 waits 1 0 : 3 waits 1 1 : do not set cs2 wait expansion bit (1) b7 b6 0 0 : 1 wait 0 1 : 2 waits 1 0 : 3 waits 1 1 : do not set cs3 wait expansion bit (1) cse00w rw cse01w rw cse10w rw cse11w rw cse20w rw cse21w rw cse30w rw cse31w rw note : rej09b0392-0064 rev.0.64 oct 12, 2007 page 63 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus notes: 1. to use the rdy signal, set the csiw bit to 0 (with wait state). 2. to access in multiplexed bus mode, se t the csiw bit to 0 (with wait state). 3. when the pm17 bit is set to 1 and accesses an exte rnal area, set the csiw bit to 0 (with wait state). 4. after reset, the pm17 bit is set to 0 (without wait state), bits cs0w to cs3w are set to 0 (with wait state), and the cse register is set to 00h (one wait state for cs0 to cs3 ). therefore, all external areas are accessed with one wait state. table 8.9 bits and bus cycles related to software wait (external area) area bus mode setting of software-wait-related bits software wait bus cycle pm1 regis- ter pm17 bit csr register csiw bit (1) cse register bits csei1w to csei0w external area separate bus 0 1 00b no wait 1 bclk cycle (read) 2 bclk cycles (write) -0 00b1 wait 2 bclk cycles (4) - 0 01b 2 waits 3 bclk cycles - 0 10b 3 waits 4 bclk cycles 1 0 (3) 00b 1 wait 2 bclk cycles multiplexed bus - 0 (2) 00b 1 wait 3 bclk cycles - 0 (2) 01b 2 waits 3 bclk cycles - 0 (2) 10b 3 waits 4 bclk cycles 1 0 (2, 3) 00b 1 wait 3 bclk cycles i = 0 to 3 ? indicates that either 0 or 1 can be set. rej09b0392-0064 rev.0.64 oct 12, 2007 page 64 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus figure 8.7 typical bus timings using software wait (1) bclk read signal write signal data bus address bus address address output input address address bus cycle (1) bus cycle (1) (1) separate bus, no wait setting (2) separate bus, 1-wait setting output input note : 1. these example timing charts indicate bus cycle length. after this bus cycle sometimes come read and write cycles in succession. bus cycle (1) bus cycle (1) (3) separate bus, 2-wait setting output address address bus cycle (1) bus cycle (1) input bclk bclk cs read signal write signal data bus address bus cs cs read signal write signal data bus address bus rej09b0392-0064 rev.0.64 oct 12, 2007 page 65 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 8. bus figure 8.8 typical bus timings using software wait (2) address address data output address address input bus cycle (1) bus cycle (1) (1) separate bus, 3-wait setting read signal write signal address bus/ data bus cs address bus ale (3) multiplexed bus, 3-wait setting output note : 1. these example timing charts indica te bus cycle length. afte r this bus cycle sometimes come read and wr ite cycles in succession. bus cycle (1) bus cycle (1) input address address address bus/ data bus address address data output address address input ale bus cycle (1) (2) multiplexed bus, 1- or 2-wait setting bus cycle (1) bclk cs bclk cs bclk write signal read signal data bus address bus write signal read signal address bus rej09b0392-0064 rev.0.64 oct 12, 2007 page 66 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 9. memory space expansion function 9. memory space expansion function the following describes a memory space expansion function. during memory expansion or microprocessor mode, the memory space expansion function allows the access space to be expanded using the appropriate register bits. table 9.1 shows setting of memory sp ace expansion function, memory space. 9.1 1-mbyte mode in this mode, the memory space is 1 mbyte. in 1-mbyte mode, the external area to be accessed is speci- fied using the csi (i = 0 to 3) signals (hereafter referred to as the csi area). figures 9.2 and 9.3 show the memory mapping and cs area in 1-mbyte mode. 9.2 4-mbyte mode in this mode, the memory space is 4 mbytes. figure 9.1 shows the dbr register. bits bsr2 to bsr0 in the dbr register select a bank number which is to be accessed to read or write data. setting the ofs bit to 1 (with offset) allows the accessed address to be offset by 40000h. in 4-mbyte mode, the csi (i = 0 to 3) pin function differs depending on an area to be accessed. 9.2.1 addresses 04000h to 3ffffh, c0000h to fffffh ? the csi signal is output from the csi pin (same operation as 1-mbyte mode; however, the last address of the cs1 area is 3ffffh). 9.2.2 addresses 40000h to bffffh ? the cs0 pin outputs ?l? ?pins cs1 to cs3 output the setting values of bits bsr2 to bsr0 (bank number) figures 9.4 and 9.5 show the memory mapping and cs area in 4-mbyte mode. note that banks 0 to 6 are data-only areas. locate the program in bank 7 or the csi area. table 9.1 setting of memory space expansion function, memory space memory space expansion function setting (pm15 to pm14) memory space 1-mbyte mode 00b 1 mbyte (no expansion) 4-mbyte mode 11b 4 mbytes rej09b0392-0064 rev.0.64 oct 12, 2007 page 67 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 9. memory space expansion function figure 9.1 dbr register no register bits. if necessary, set to 0. read as 0 b7 b6 b5 b4 b1 b2 b3 data bank register (1) symbol dbr address 000bh bit symbol bit name rw after reset 00h b0 function rw 1. effective when bits pm01 and pm00 in the pm0 regist er are set to 01b (memory expansion mode) or 11b (microprocessor mode). bsr0 bank selection bits ? (b1-b0) ? ofs rw ? (b7-b6) ? offset bit 0 : not offset 1 : offset rw bsr1 rw bsr2 b5 b4 b3 0 0 0 : bank 0 0 1 0 : bank 2 1 0 0 : bank 4 1 1 0 : bank 6 b5 b4 b3 0 0 1 : bank 1 0 1 1 : bank 3 1 0 1 : bank 5 1 1 1 : bank 7 no register bits. if necessary, set to 0. read as 0 note : rej09b0392-0064 rev.0.64 oct 12, 2007 page 68 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 9. memory space expansion function figure 9.2 memory mapping and cs area in 1-mbyte mode (pm13 = 0) figure 9.3 memory mapping and cs area in 1-mbyte mode (pm13 = 1) microprocessor mode 00000h 00400h xxxxxh yyyyyh fffffh d0000h 08000h memory expansion mode sfr internal ram internal rom reserved area reserved area cs3 (16 kbytes) cs1 (32 kbytes) cs0 (microprocessor mode : 832 kbytes) 28000h 30000h 04000h reserved area 27000h capacity address yyyyyh 128 kbytes e0000h 256 kbytes d0000h (1) capacity address xxxxxh 12 kbytes 033ffh 16 kbytes 03fffh (1) 512 kbytes d0000h (1) pm13 = 0 external area 0d000h sfr internal ram reserved area reserved area external area external area cs2 (20 kbytes) cs0 (memory expansion mode : 640 kbytes ) internal ram internal rom cs0 memory expansion mode 30000h to cffffh external area cs1 microprocessor mode 30000h to fffffh 28000h to 2ffffh cs2 08000h to 0cfffh 0d800h to 26fffh note that this applies to the following areas only in the conditions described below. in memory expansion mode or when pm10 = 0, 08000h to 0cfffh when pm10 = 0, 0e000h to 0ffffh when prg2c0 = 1 10000h to 13fffh cs3 04000h to 07fffh 31 kbytes 03fffh (1) notes : 1. when the pm13 bit in the pm1 register is set to 0, 15 kbytes of the internal ram and 192 kbytes of the internal rom can be u sed. 2. when the pm10 bit is set to 0, this area is used as external area; when 1, reserved area. 3. when the pm10 bit is set to 0, this area is used as external area; when 1, internal rom (data flash). 4. when the prg2c0 bit in the prg2c register is set to 1, this area is used as external area; when 0, internal rom (program rom 2). 5. when the prg2c0 bit in the prg2c register is set to 1, this area is used as external area; when 0, reserved area. 0d800h 10000h 0e000h 14000h prpgram rom 2 (4) data flash (3) sfr reserved, external area (5) reserved, external area (2) sfr cs2 (76 kbytes) (8 kbytes) (16 kbytes) (2 kbytes) cs2 cs2 cs2 cs2 (102 kbytes ) capacity address yyyyyh 128 kbytes e0000h 256 kbytes c0000h capacity address xxxxxh 12 kbytes 033ffh 16 kbytes 043ffh pm13 = 1 internal ram internal rom cs0 memory expansion mode 30000h to 7ffffh external area cs1 microprocessor mode 30000h to fffffh 28000h to 2ffffh cs2 0d800h to 26fffh note that this applies to the following areas only in the conditions described below. when pm10 = 0, 0e000h to 0ffffh when prg2c0 = 1, 10000h to 13fffh cs3 no area notes : 1. when the pm10 bit is set to 0, this area is used as external area; when 1, internal rom (data flash). 2. when the prg2c0 bit in the prg2c register is set to 1, this area is used as external area; when 0, internal rom (program rom 2). 3. when the pm10 bit is set to 0, this area is used as external area; when 1, reserved area. 4. when the prg2c0 bit in the prg2c register is set to 1, this area is used as external area; when 0, reserved area. microprocessor mode 00000h 00400h xxxxxh yyyyyh fffffh 80000h 08000h memory expansion mode sfr internal ram internal rom reserved area reserved area cs1 (32 kbytes) cs0 (misropocessor mode : 832 kbytes) 28000h 30000h reserved area 27000h external area 0d000h sfr internal ram reserved area reserved area external area cs0 (memory expansion mode : 320 kbytes) 0d800h 10000h 0e000h 14000h program rom 2 (2) data flash (1) sfr reserved, external area (4) reserved, external area (3) sfr cs2 (76 kbytes) (8 kbytes) (16 kbytes) (2 kbytes) cs2 cs2 cs2 cs2 (102 kbytes) rej09b0392-0064 rev.0.64 oct 12, 2007 page 69 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 9. memory space expansion function figure 9.4 memory mapping and cs area in 4-mbyte mode (pm13 = 0) figure 9.5 memory mapping and cs area in 4-mbyte mode (pm13 = 1) pm13 = 0 cs0 memory expansion mode c0000h to cffffh external area cs1 microprocessor mode c0000h to fffffh 28000h to 3ffffh cs2 08000h to 0cfffh 0d800h to 26fffh note that this applies to the following areas only in the conditions described below. inmemory expansion mode or when pm10 = 0, 08000h to 0cfffh when pm10 = 0, 0e000h to 0ffffh: when prg2c0 = 1, 10000h to 13fffh cs3 04000h to 07fffh 40000h to bffffh other than the cs area (1) notes : 1. the cs0 pin outputs a low signal, and pins cs1 to cs3 output a bank number. 2. when the pm13 bit is set to 0, 15 kbytes of the internal ram and 192 kbytes of the internal rom can be used. 3. when the pm10 bit is set to 0, this area is used as external area; when 1, reserved area. 4. when the pm10 bit is set to 0, this area is used as external area; when 1, internal rom (data flash). 5. when the prg2c0 bit in the prg2c register is set to 1, this ar ea is used as external area; when 0, internal rom (program rom 2). 6. when the prg2c0 bit in the prg2c register is set to 1, this area is used as external area; when 0, reserved area. capacity address yyyyyh 128 kbytes e0000h 256 kbytes d0000h (2) capacity address xxxxxh 12 kbytes 033ffh 16 kbytes 03fffh (2) 512 kbytes d0000h (2) internal ram internal rom 31 kbytes 03fffh (2) microprocessor mode 00000h 00400h xxxxxh yyyyyh fffffh d0000h 08000h memory expansion mode sfr internal ram internal rom reserved area reserved area cs3 (16 kbytes) cs1 (96 kbytes) cs0 (misropocessor mode : 256 kbytes) 28000h 40000h 04000h reserved area 27000h external area 0d000h sfr internal ram reserved area reserved area external area external area cs2 (20 kbytes) other than the cs area (512 kbytes x 8 banks) 0d800h 10000h 0e000h 14000h program rom 2 (5) data flash (4) sfr reserved, external area (6) reserved, external area (3) sfr cs2 (76 kbytes) (8 kbytes) (16 kbytes) (2 kbytes) cs2 cs2 cs2 cs2 (102 kbytes) cs0 (memory expansion mode : 64 kbytes) c0000h pm13 = 1 cs0 external area cs1 microprocessor mode c0000h to fffffh 28000h to 3ffffh cs2 0d800h to 26fffh note that this applies to the following areas only in the conditions described below. when pm10 = 0, 0e000h to 0ffffh when prg2c0 = 1, 10000h to 13fffh cs3 no area other than the cs area (1) memory expansion mode 40000h to 7ffffh microprocessor mode 40000h to bffffh notes : 1. the cs0 pin outputs a low signal, and pins cs1 to cs3 output a bank number. 2. when the pm10 bit is set to 0, this area is used as external area; when 1, internal rom (data flash). 3. when the prg2c0 bit in the prg2c register is set to 1, this area is used as external area; when 0, internal rom (program rom 2). 4. when the pm10 bit is set to 0, this area is used as external area; when 1, reserved area. 5. when the prg2c0 bit in the prg2c register is set to 1, this area is used as external area; when 0, reserved area. capacity address yyyyyh 128 kbytes e0000h 256 kbytes c0000h capacity address xxxxxh 12 kbytes 16 kbytes 512 kbytes 80000h internal ram internal rom 31 kbytes 033ffh 043ffh 07fffh microprocessor mode 00000h 00400h xxxxxh yyyyyh fffffh 08000h memory expansion mode sfr internal ram internal rom reserved area reserved area cs1 (96 kbytes) cs0 (misropocessor mode: 256 kbytes) 28000h 40000h reserved area 27000h external area 0d000h sfr internal ram reserved area reserved area external area other than the cs area (memory expansion mode: 256 kbytes x 8 banks) * change offset to use 256 kbytes x 8 banks x2 0d800h 10000h 0e000h 14000h program rom 2 (3) data flash (2) sfr reserved, external area (5) reserved, external area (4) sfr cs2 (76 kbytes) (8 kbytes) (16 kbytes) (2 kbytes) cs2 cs2 cs2 cs2 (102 kbytes) c0000h 80000h other than the cs area (microprocessor mode: 512 kbytes x 8 banks) rej09b0392-0064 rev.0.64 oct 12, 2007 page 70 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 9. memory space expansion function figure 9.6 shows the external memory connect example in 4-mbyte mode. in this example, the cs pin of 4-mbyte rom is connected to the cs0 pin of the microcomputer. the 4- mbyte rom address input pins ad21, ad20, and ad19 are connected to pins cs3 , cs2 , and cs1 of the microcomputer, respectively. the address input ad18 pin is connected to the a19 pin of microcom- puter. figures 9.7 to 9.9 show the relationship of addr esses between the 4-mbyte rom and the micro- computer for the case of a connection example in figure 9.6. in microprocessor mode or in memory expansion mo de where the pm13 bit in the pm1 register is 0, banks are located every 512 kbytes. setting the ofs bi t in the dbr register to 1 (offset) allows the accessed address to be offset by 40000h, so that even the data overlapping at a bank boundary can be accessed in succession. in memory expansion mode where the pm13 bit is 1, each 512-kbyte bank can be accessed in 256 kbyte units by switching them over with the ofs bit. because the sram can be accessed on condition that the chip select signals s2 = ?h? and s1 = ?l?, cs0 and cs2 can be connected to s2 and s1 , respectively. if the sram does not have the input pins which accept ?h? active and ?l? active chip select signals ( s1 , s2), cs0 and cs2 should be decoded external to the chip. figure 9.6 external memory connect example in 4-mbyte mode 17 8 microcomputer d0 to d7 a0 to a16 a17 rd wr cs1 cs2 cs3 cs0 a19 4-mbyte rom dq0 to dq7 ad0 to ad16 ad17 ad18 ad19 oe cs 128-kbyte sram dq0 to dq7 ad0 to ad16 s2 w oe s1 ad20 ad21 note : 1. if only one chip select pin (s1 or s2) is present, using an external circuit is required for decode. (1) rej09b0392-0064 rev.0.64 oct 12, 2007 page 71 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 9. memory space expansion function figure 9.7 relationship between addresses on 4-mbyte rom and those on microcomputer (1) a20 a19 a18 n.c. a17 a16 a15 to a0 address input for 4-mbyte rom 4-mbyte rom access area a18 cs output address output ofs access area output from the microcomputer pins cs3 cs2 cs1 a19 a17 a16 a15 to a0 40000h 0 000000h bank number 0 bffffh 040000h 1 080000h 0 0c0000h 1 100000h 0 140000h 1 180000h 0 1c0000h 1 200000h 0 240000h 1 280000h 0 2c0000h 1 300000h 0 340000h 1 40000h 380000h 0 80000h 3c0000h c0000h 3c0000h d0000h internal rom access internal rom access internal rom access internal rom access a21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 7ffffh bffffh cffffh dffffh d0000h dffffh 07ffffh 0bffffh 0fffffh 13ffffh 17ffffh 1bffffh 1fffffh 23ffffh 27ffffh 2bffffh 2fffffh 33ffffh 37ffffh 3bffffh 3bffffh 3fffff h 3cffffh 0 1 2 3 4 5 6 7 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh rom address microcomputer address ofs bit in dbr register = 0 ofs bit in dbr register = 1 memory expansion mode where pm13 = 0 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 000000h 080000h 100000h 180000h 200000h 280000h 380000h 3fffffh 40000h bffffh 3c0000h 340000h 2c0000h 240000h 1c0000h 140000h 0c0000h 040000h bank 1 (512 kbytes) bank 3 (512 kbytes) bank 4 (512 kbytes) bank 5 (512 kbytes) bank 6 (512 kbytes) data only program or data 300000h bank 0 (512 kbytes) 40000h 40000h 40000h 40000h 40000h 40000h 40000h bffffh bffffh bffffh bffffh bffffh bffffh program or data bffffh bank 0 (512 kbytes) bank 1 (512 kbytes) bank 2 (512 kbytes) bank 3 (512 kbytes) bank 4 (512 kbytes) bank 5 (512 kbytes) bank 6 (512 kbytes) bank 7 (512 kbytes) bank 2 (512 kbytes) rej09b0392-0064 rev.0.64 oct 12, 2007 page 72 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 9. memory space expansion function figure 9.8 relationship between addresses on 4-mbyte rom and those on microcomputer (2) a20 a19 a18 n.c. a17 a16 a15 to a0 address input for 4-mbyte rom 4-mbyte rom access area a18 cs output address output ofs access area output from the microcomputer pins cs3 cs2 cs1 a19 a17 a16 a15 to a0 000000h bank number 07ffffh 080000h 0c0000h 100000h 140000h 180000h 1c0000h 200000h 240000h 280000h 2c0000h 300000h 340000h 380000h internal rom access 3c0000h internal rom access internal rom access internal rom access a21 03ffffh 040000h 0bffffh 0fffffh 13ffffh 17ffffh 1bffffh 1fffffh 23ffffh 27ffffh 2bffffh 2fffffh 33ffffh 37ffffh 3bffffh 3fffffh 0 1 2 3 4 5 6 7 7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7ffffh 80000h 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h fffffh 80000h 7ffffh 40000h fffffh 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 1 1 1 0 0 memory expansion mode where pm13 = 1 rom address microcomputer address 000000h 080000h 100000h 180000h 200000h 280000h 380000h 3fffffh 40000h 7ffffh 3c0000h 340000h 2c0000h 240000h 1c0000h 140000h 0c0000h 040000h bank 0 (256 kbytes) bank 1 (256 kbytes) bank 1 (256 kbytes) bank 2 (256 kbytes) bank 2 (256 kbytes) bank 3 (256 kbytes) bank 3 (256 kbytes) bank 4 (256 kbytes) bank 4 (256 kbytes) bank 5 (256 kbytes) bank 5 (256 kbytes) bank 6 (256 kbytes) bank 6 (256 kbytes) bank 7 (256 kbytes) data only 300000h bank 0 (256 kbytes) ofs bit in dbr register = 0 ofs bit in dbr register = 1 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh 40000h 7ffffh program or data bank 7 (256 kbytes) 40000h 7ffffh data only rej09b0392-0064 rev.0.64 oct 12, 2007 page 73 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 9. memory space expansion function figure 9.9 relationship between addresses on 4-mbyte rom and those on microcomputer (3) a20 a19 a18 n.c. a17 a16 a15 to a0 address input for 4-mbyte rom 4-mbyte rom access area a18 cs output address output ofs access area output from the microcomputer pins cs3 cs2 cs1 a19 a17 a16 a15 to a0 bank number a21 0 1 2 3 4 5 6 7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 000000h 040000h 080000h 0c0000h 100000h 140000h 180000h 1c0000h 200000h 240000h 280000h 2c0000h 300000h 340000h 380000h 3c0000h 3c0000h 07ffffh 0bffffh 0fffffh 13ffffh 17ffffh 1bffffh 1fffffh 23ffffh 27ffffh 2bffffh 2fffffh 33ffffh 37ffffh 3bffffh 3bffffh 3fffffh 3fffffh 40000h 80000h c0000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h 7ffffh bffffh fffffh 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0000h ffffh 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 microprocessor mode rom address microcomputer address ofs bit in dbr register = 0 ofs bit in dbr register = 1 000000h 080000h 100000h 180000h 200000h 280000h 380000h 3fffffh 40000h bffffh 3c0000h 340000h 2c0000h 240000h 1c0000h 140000h 0c0000h 040000h data only program or data 300000h 40000h 40000h 40000h 40000h 40000h 40000h 40000h bffffh bffffh bffffh bffffh bffffh bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh 40000h bffffh program or data fffffh 7ffffh c0000h bank 0 (512 kbytes) bank 1 (512 kbytes) bank 2 (512 kbytes) bank 3 (512 kbytes) bank 2 (512 kbytes) bank 1 (512 kbytes) bank 0 (512 kbytes) bank 3 (512 kbytes) bank 4 (512 kbytes) bank 4 (512 kbytes) bank 5 (512 kbytes) bank 6 (512 kbytes) bank 5 (512 kbytes) bank 7 (512 kbytes) bank 6 (512 kbytes) rej09b0392-0064 rev.0.64 oct 12, 2007 page 74 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 10. clock generation circuit 10. clock generation circuit 10.1 type of the clock generation circuit 4 circuits are incorporated to generate the system clock signal: ? main clock oscillation circuit ? sub clock oscillation circuit ? 125 khz on-chip oscillator ? pll frequency synthesizer table 10.1 lists the clock generation circuit specif ications. figure 10.1 shows the system clock gener- ation circuit. figures 10.2 to 10.6 show the clock-related registers. note: 1. the pll frequency synthesizer uses the main cloc k oscillation circuit as a reference clock source. the items above are based on those of the main clock oscillation circuit. table 10.1 clock generation circuit specifications item main clock oscillation circuit sub clock oscillation circuit 125 khz on-chip oscillator pll frequency synthesizer use of clock cpu clock source peripheral function clock source cpu clock source clock source of timer a and b. cpu clock source peripheral function clock source cpu and peripheral function clock sources when the main clock stops oscillating cpu clock source peripheral function clock source clock frequency 0 to 20 mhz 32.768 khz about 125 khz 10 to 25 mhz usable oscillator c eramic oscillator crystal oscillator crystal oscillator - - (1) pins to connect oscillator xin, xout xcin, xcout - - (1) oscillation stop, restart function presence presence p resence presence oscillator status after reset oscillating stopped oscillating stopped other externally derived clock can be input - - (1) rej09b0392-0064 rev.0.64 oct 12, 2007 page 75 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 10. clock generation circuit figure 10.1 system clock generation circuit fc32 cm02, cm04, cm05, cm06, cm07 : bits in the cm0 register cm10, cm11, cm14, cm16, cm17 : bits in the cm1 register pclk0, pclk1 : bits in the pclkr register cm21, cm27 : bits in the cm2 register xout main clock oscillation circuit fc cm02 cm04 cm10 = 1 (stop mode) q s r wait instruction cm05 q s r fc cpu clock cm07 = 0 cm07 = 1 divider a 1/2 1/2 1/2 1/2 cm06 = 0 cm17 to cm16 = 00b cm06 = 0 cm17 to cm16 = 01b cm06 = 0 cm17 to cm16 = 10b cm06 = 1 cm06 = 0 cm17 to cm16 = 11b d a details of the divider subclock oscillation circuit xcin xcout xin c b b 1/2 c 1/2 1/4 1/8 1/16 1/32 pll frequency synthesizer 0 1 cm21=1 cm11 cm21=0 125 khz on-chip oscillator pll clock subclock 125 khz on-chip oscillator clock bclk main clock clkout pm01 to pm00 = 00b, cm01 to cm00 = 01b pm01 to pm00 = 00b, cm01 to cm00 = 10b cm01 to cm00 = 00b i/o ports pm01 to pm00 = 00b, cm01 to cm00 = 11b oscillation stop, re-oscillation detection circuit cm14 d4int clock foco-s f8 f32 f1 1/32 d software reset nmi interrupt request level judgement output reset pm24 brown-out reset watchdog timer reset oscillation stop detect reset pm25 oscillation stop detection reset main clock oscillation stop, re-oscillation detection circuit oscillation stop, re-oscillation detection interrupt signal cm21 switch signal cm27 = 0 cm27 = 1 charge / discharge circuit reset generating circuit oscillation stop, re-oscillation detection interrupt generating circuit pulse generation circuit for clock edge detection and charge / discharge control phase comparator charge pump voltage control oscillator (vco) pll clock main clock divider 1/32 internal lowpass filter pll frequency synthesizer reference clock divider rej09b0392-0064 rev.0.64 oct 12, 2007 page 76 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 10. clock generation circuit figure 10.2 cm0 register b7 b6 b5 b4 b1 b2 b3 system clock control register 0 (1) symbol cm0 address 0006h bit symbol bit name rw cm00 after reset 01001000b rw notes : 1. rewrite this register after setting the prc0 bit in the prcr register to 1 (write enabled). 2. the cm03 bit is set to 1 (high) while the cm04 bi t is set to 0 (i/o port) or when entering stop mode. 3. this bit is provided to stop the main clock when the low power consumption mode or 125 khz on-chip oscillator low power dissipation mode is selected. this bit cann ot be used for detection as to whether the main clock stops or not. to stop the main clock, set bits as follows: (a) set the cm07 bit to 1 (sub clock selected) with the sub-clock stably oscillates, or set the cm21 bit in the cm2 register to 1 (125 khz on-chip oscillator selected). (b) set the cm20 bit in the cm2 register to 0 (o scillation stop, re-oscillation detection function disabled). (c) set the cm05 bit to 1 (stop). 4. during external clock input, set the cm05 bit to 0 (oscillate). 5. when the cm05 bit is set to 1, the xout pin is he ld ?h?. because the internal feedback resistor remains connected, the xin pin is pulled ?h? to the same level as xout via the feedback resistor. 6. after setting the cm04 bit to 1 (xcin-xcout oscillator function), wait until the sub-clock oscillates stably before switching the cm07 bit from 0 to 1 (sub clock). 7. when entering stop mode, the cm06 bit is set to 1 (divide-by-8 mode). 8. the fc32 and foco-s clock do not stop. 9. to use a sub-clock, set this bit to 1. also make sure ports p8_6 and p8_7 are directed for input, with no pull- ups. 10. when the pm21 bit in the pm2 register is set to 1 (disable clock modification), this bit remains unchanged even if writing to bits cm02, cm05, and cm07. 11. when setting the pm21 bit to 1, set the cm07 bit to 0 (main clock) before setting the pm21 bit to 1. 12. to use the main clock as the clock source for the cpu clock, set bits as follows. (a) set the cm05 bit to 0 (oscillate). (b) wait the main clock oscillation stabilizes. (c) set bits cm11, cm21, and cm07 to 0. 13. when the cm07 bit is set to 1 (sub clock) and the cm05 bit is set to 1 (main clock stops), the cm06 bit is fixed to 1 (divide-by-8 mode) an d the cm15 bit is fixed to 1 (drive capacity high). 14. to return from 125 khz on-chip oscillator mode to high-speed or middle-speed mode, set bits cm06 and cm15 to 1. b0 function b1 b0 0 0 : i/o port p5_7 0 1 : output fc 1 0 : output f8 1 1 : output f32 clock output function select bit (valid only in single-chip mode) cm01 cm02 wait mode peripheral function clock stop bit (10) 0 : peripheral function clock f1 does not stop in wait mode 1 : peripheral function clock f1 stops in wait mode (8) cm03 xcin-xcout drive capacity select bit (2) 0 : low 1 : high cm04 port xc select bit (2) 0 : i/o ports p8_6, p8_7 1 : xcin-xcout oscillation function (9) cm05 main clock stop bit (3, 4, 10, 12, 13) 0 : on 1 : off (5) cm06 main clock division select bit 0 (7, 13, 14) system clock select bit (6, 10, 11, 12) 0 : cm16 and cm17 enabled 1 : division-by-8 mode cm07 0 : main clock, pll clock, or 125 khz on- chip oscillator clock 1 : sub clock rw rw rw rw rw rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 77 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit figure 10.3 cm1 register b7 0 0 b6 b5 b4 b1 b2 b3 system clock control register 1 (1) symbol cm1 address 0007h bit symbol bit name rw cm10 after reset 00100000b notes : 1. rewrite this register after setting the prc0 bit in the prcr register to 1 (write enabled). 2. when entering stop mode or the cm05 bit is set to 1 (main clock stops) in low speed mode, the cm15 bit is set to 1 (drive capacity high). 3. this bit is valid when the cm06 bit is set to 0 (bits cm16 and cm17 enabled). 4. if the cm10 bit is set to 1 (stop mode), xout is held ?h? and the internal feedback resistor is disconnected. pins xcin and xcout are in high-impedance state. when the cm11 bit is set to 1 (pll clock), or the cm20 bit in the cm2 register is set to 1 (oscillation stop detection function enabled), do not set the cm10 bit to 1. 5. after setting the plc07 bit in the plc0 register to 1 (pll operation), wait tsu (p ll) elapses before setting the cm11 bit to 1 (pll clock). 6. when the pm21 bit in the pm2 register is set to 1 (dis able clock modification), this bit remains unchanged even if writing to bits cm10 and cm11. when the cspro bit in the cspr register is set to 1 (count source protection mode), this bit remains unchanged even if writing to the cm10 bit. 7. the cm11 bit is valid when bits cm07 and cm21 are set to 0. 8. the cm14 bit can be set to 1 (125 khz on-chip oscillator off) when the cm21 bit is set to 0 (main clock or pll clock). when the cm21 bit is set to 1 (125 khz on-chip oscillator clock), the cm14 bit is set to 0 (125 khz on-chip oscillator on) and remains uncha nged even if writing 1 to this bit. 9. when the cspro bit in the cspr register is set to 1 (count source protection mode), the cm14 bit is automatically set to 0 (125 khz on-chip oscillator on) and remains unchanged even if writing a 1 to this bit (125 khz on-chip oscillator does not stop). b0 function all clock stop control bit (4, 6) ? (b3-b2) cm14 reserved bits 0 : clock on 1 : all clocks off (stop mode) cm15 set to 0 cm16 0 : 125 khz on-chip oscillator on 1 : 125 khz on-chip oscillator off rw 0 : low 1 : high 125 khz on-chip oscillator stop bit (8, 9) xin-xout drive capacity select bit (2) rw rw rw rw cm11 system clock select bit 1 (6, 7) 0 : main clock 1 : pll clock (5) rw cm17 main clock division select bit 1 (3) b7 b6 0 0 : no division mode 0 1 : divide-by-2 mode 1 0 : divide-by-4 mode 1 1 : divide-by-16 mode rej09b0392-0064 rev.0.64 oct 12, 2007 page 78 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit figure 10.4 cm2 register notes : 1. rewrite this register after setting the prc0 bi t in the prcr register to 1 (write enabled). 2. when the cm20 bit is set to 1 (oscillation stop and re-oscillation detection function enabled), the cm27 bit is set to 1 (oscillation stop and re-oscill ation detection interrupt), and the cpu clock source is the main clock, the cm21 bit is set to 1 (125 khz on-chip oscillator clock) if the main clock stop is detected. 3. if the cm20 bit is set to 1 and the cm23 bit is set to 1 (main clock stops), do not set the cm21 bit to 0. 4. this bit is set to 1 when the main clock stop is detected and the main cl ock re-oscillation is detected. when this flag changes state from 0 to 1, an oscillation stop or a re-oscillation detection interrupt is generated. use this bit in an interrupt routine to determine the factor s of interrupts between the oscillation stop, re-oscillation etection interrupt and the watchdog timer interrupt. this bit is set to 0 by writing 0 in a program. (this bit remains unchanged even if a 1 is written. nor is it set to 0 when an oscillation stop or a re-oscillation detection interrupt request is acknowledged.) when the cm22 bit is set to 1 and an oscillation stop or a re- oscillation is detected, an oscill ation stop or a re-oscillation detection interrupt is not generated. 5. determine the main clock status by reading the cm23 bi t several times in an oscillation stop or a re-oscillation detection interrupt routine. 6. this bit is valid when the cm07 bit in the cm0 register is set to 0. 7. when the pm21 bit in the pm2 register is set to 1 (disable clock modification), this bit remains unchanged even if writing to the cm20 bit. 8. when the cm20 bit is set to 1 (oscillation stop and re -oscillation detection function enabled), the cm27 bit is 1 (oscillation stop and re-oscillation detection interrupt), and the cm11 bit is set to 1 (pll clock is selected as the cpu clock source), the cm21 bit remains unchanged even if a main clock stop is detected. when the cm22 bit is set to 0 under these conditions, an oscillation stop, a re-oscillation detection interrupt request is generated at main clock stop detection. set the cm21 bit to 1 (125 khz on-chip oscillator clock) in the interrupt routine. 9. set the cm20 bit to 0 (disabled) before entering stop mode. exit stop mode before setting the cm20 bit back to 1 (enabled). 10. set the cm20 bit in the cm2 register to 0 (disabled) before setting the cm05 bit in the cm0 register to 1 (main clock stops). 11. bits cm20, cm21, and cm27 remain unchanged at the oscillation stop detection reset. 12. when the cm21 bit is set to 0 (main clock or pll clock) and the cm05 bit is set to 1 (main clock stops), the cm06 bit is fixed to 1 (divide-by-8 mode) and the cm15 bit is fixed to 1 (drive capacity high). b7 0 0 b6 b5 b4 b1 b2 b3 oscillation stop detection register (1) symbol cm2 address 000ch bit symbol bit name rw after reset 0x000010b (11) b0 function cm20 oscillation stop and re-oscillation detection enable bit (7, 9, 10,11) 0: oscillation stop and re-oscillation detection function disabled 1: oscillation stop and re-oscillation detection function enabled rw cm21 system clock select bit 2 (2, 3, 6, 8, 11, 12) rw 0: main clock or pll clock 1: 125 khz on-chip oscillator clock cm22 oscillation stop and re-oscillation detection flag (4) rw 0: main clock stops and re-oscillation not detected 1: main clock stops and re-oscillation detected cm23 xin monitor flag (5) ro 0: main clock oscillates 1: main clock stops ? (b5-b4) reserved bits set to 0 rw ? (b6) no register bit. if necessary, set to 0. read as undefined value ? cm27 operation select bit (when an oscillation stops and re-oscillation is detected) (11) 0: oscillation stop detection reset 1: oscillation stop, re-oscillation detection interrupt rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 79 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit figure 10.5 pclkr register and pm2 register peripheral clock select register (1) b7 0 0 0 0 0 0 b6 b5 b4 b1 b2 b3 symbol pclkr address 0012h bit symbol bit name rw after reset 00000011b b0 function ? (b7-b2) rw reserved bits set to 0. read as undefined value note : 1. write to this register after setting the prc0 bit in the prcr register to 1 (write enabled). pclk0 timers a and b clock select bit (clock source for timers a , b, and the dead time timer) 0 : f2timab 1 : f1timab rw pclk1 rw si/o clock select bit (clock source for uart0 to uart2, uart5 to uart7, si/ o3, and si/o4) 0 : f2sio 1 : f1sio b7 0 b6 b5 b4 b1 b2 b3 processor mode register 2 (1) symbol pm2 address 001eh bit symbol bit name rw after reset xx000x01b notes : 1. write to this register after setting the prc1 bit in the prcr register to 1 (write enabled). 2. the pm20 bit becomes effective when the plc07 bit in the plc0 register is set to 1 (pll on). change the pm20 bit when the plc07 bit is set to 0 (pll off). 3. once this bit is set to 1, it cannot be cleared to 0 in a program. 4. if the pm21 bit is set to 1, writing to the following bits has no effect: cm02 bit in cm0 register cm05 bit in cm0 register (main clock does not stop) cm07 bit in cm0 register (clock source for the cpu clock does not change) cm10 bit in cm1 register (stop mode is not entered) cm11 bit in cm1 register (clock source for the cpu clock does not change) cm20 bit in cm2 register (oscillation stop and re-oscillation detection function settings do not change) all bits in plc0 register (pll frequency synthesizer settings do not change) be aware that the wait instruction cannot be executed when the pm21 bit = 1. 5. when using low voltage detection interrupt, set the pm25 bit to 1 (provide enabled). b0 function pm20 specifying wait when accessing sfr at pll operation (2) 0 : 2 waits 1 : 1 wait rw ? (b2) ? (b3) pm24 set to 0 0 : port p8_5 function 1 : nmi function reserved bit p8_5 / nmi function select bit (3) rw rw pm21 system clock protection bit (3, 4) 0 : clock is protected by prcr register 1 : clock modification disabled rw no register bit. if necessary, set to 0. read as undefined value ? ? (b7-b6) no register bits. if necessary, set to 0. read as undefined value ? pm25 0 : provide enabled 1 : provide disabled d4int clock provide enable bit (5) rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 80 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit figure 10.6 plc0 register b7 b6 b5 b4 b1 b2 b3 pll control register 0 (1, 2) symbol plc0 address 001ch bit symbol bit name rw after reset 0x01x010b notes : 1. write to this register after setting the prc0 bit in the prcr register to 1 (write enabled). 2. when the pm21 bit in the pm2 register is 1 (clock modi fication disabled), writing to this register has no effect. 3. bits plc00 to plc02, plc04, and plc5 can only be modified when the plc07 bit = 0 (pll turned off). the value once written to this bit cannot be modified. 4. before setting the plc07 bit to 1, set the cm05 bit to 0 (main clock oscillation). b0 function ? (b3) plc04 rw plc05 rw ? (b6) plc07 no register bit. if necessary, set to 0. read as undefined value 0 : pll off 1 : pll on operation enable bit (4) reserved bit read as undefined value reference frequency counter set bit (3) b5 b4 0 0 : no division 0 1 : divide-by-2 1 0 : divide-by-4 1 1 : do not set plc00 pll multiplying factor select bit (3) plc01 plc02 b2 b1 b0 0 0 0 : do not set 0 0 1 : multiply by 2 0 1 0 : multiply by 4 0 1 1 : multiply by 6 1 0 0 : multiply by 8 1 0 1 : 1 1 0 : do not set 1 1 1 : rw rw rw ro rw ? rej09b0392-0064 rev.0.64 oct 12, 2007 page 81 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit the following describes the clocks gener ated by the clock generation circuit. 10.1.1 main clock this clock is provided by the ma in clock oscillation circuit and used as the clock source for the cpu and peripheral function clocks. the main clock oscillation circuit is c onfigured by connecting a resonator between pins xin and xout. the main clock oscillation circuit cont ains a feedback resistor, which is dis- connected from the oscillation circui t during stop mode in order to re duce the amount of power consumed in the chip. the main clock oscillation circuit may also be configured by feed ing an externally generated clock to the xin pin. figure 10.7 shows the examples of main clock connection circuit. the power consumption in the chip can be reduced by setting the cm05 bit in the cm0 register to 1 (main clock oscillation circuit turned off) after switching the clock source for the cpu clock to a sub clock or 125 khz on-chip oscillation clock. in this case, xout goes ?h?. furthermore, because the internal feedback resistor remains on, xin is pulled ?h? to xout via the feedback resistor. during stop mode, all clocks including th e main clock are turned off. refer to 10.4 ?power control? for details. figure 10.7 examples of main clock connection circuit note : 1. place a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by each oscillator manufacturer. when the oscillation drive capacity is set to low, check if oscillation is stable at low. also, place a feedback resistor between xin and xout if the oscillator manufacturer recommends placing the resistor externally. external clock open vcc1 vss microcomputer (built-in feedback resistor) xin xout rd (1) cin cout vss oscillator microcomputer (built-in feedback resistor) xin xout rej09b0392-0064 rev.0.64 oct 12, 2007 page 82 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.1.2 sub clock the sub clock is genera ted by the sub clock os cillation circuit. this clock is used as the clock source for the cpu clock, as well as the timer a and timer b co unt sources. in addition, an fc clock with the same frequency as that of the sub clock can be output from the clkout pin. the sub clock oscillation circuit is configured by co nnecting a crystal resona tor between pins xcin and xcout. the sub clock oscillation circuit contains a feedback resistor, which is disconnected from the oscillation circuit during stop mode in order to reduce the amount of power consumed in the chip. the sub clock oscillation circuit may also be configured by feeding an externally generated clock to the xcin pin. figure 10.8 shows the examples of sub clock connection circuit. after reset, the sub clock is turned off. at this time, the feedback resistor is disconnected from the oscil- lation circuit. to use the sub clock for the cpu clock, set the cm07 bi t in the cm0 register to 1 (sub clock) after the sub clock becomes os cillating stably. during stop mode, all clocks including the sub clock are turned off. refer to 10.4 ?power control? for details. figure 10.8 examples of sub clock connection circuit note : 1. place a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by each oscillator manufacturer. when the oscillation drive capacity is set to low, check if oscillation is stable at low. also, place a feedback resistor between xcin and xcout if the oscillator manufacturer recommends placing the resistor externally. external clock open vcc1 vss xcin xcout rcd (1) ccin ccout vss oscillator microcomputer (built-in feedback resistor) xcin xcout microcomputer (built-in feedback resistor) rej09b0392-0064 rev.0.64 oct 12, 2007 page 83 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.1.3 125 khz on-chip osci llator clock (foco-s) this clock, approximately 125 khz, is supplied by 125 khz on-chip oscilla tor. this clock is used as the clock source for the cpu and peripheral function clo cks. in addition, if the cspro bit in the cspr reg- ister is 1 (count source protection mode enabled), this clock is used as the count source for the watch- dog timer (refer to 13.2 ?count source protection mode enabled? ). after reset, the 125 khz on-chip oscillator divided by 8 provides the cpu clock. it stops when the cm14 bit in the cm1 register is set to 0 (125 khz on-chi p oscillator stops). if the main clock stops oscillating when the cm20 bit in the cm2 register is 1 (oscillation stop, re-oscillation detection function enabled) and the cm27 bit is 1 (oscillation stop, re-oscillation detection interr upt), the 125 khz on-chip oscillator automatically starts operating and supplyi ng the necessary clock for the microcomputer. 10.1.4 pll clock the pll clock is generated by the pll frequency synthes izer. this clock is used as the clock source for the cpu and peripheral function clocks. after reset, the pll frequency synthesizer is turned off. the pll frequency synthesizer is activated by setting the plc07 bit to 1 (pll operation). when the pll clock is used as the clock source for the cpu clock, wait for tsu (pll) un til the pll clock to be stable, and then set the cm11 bit in the cm1 register to 1. before entering wait mode or stop mode, be sure to set the cm11 bit to 0 (cpu clock source is the main clock). furthermore, be fore entering stop mode, be sure to set the plc07 bit in the plc0 register to 0 (pll stops). figure 10.10 shows the procedure to use pll clock as cpu clock source. the pll clock is the main clock divided by the sele cted values of bits plc05 and plc04 in the plc0 register, and then multiplied by the selected values of bits plc02 to plc00. set bits plc05 and plc04 to fit divided frequency between 2 mhz and 5 mhz. figure 10.9 shows the relation between the main clock and the pll clock. figure 10.9 relation between the main clock and the pll clock pll clock main clock n : 1, 2, 4 (selected by bits plc05 and plc04 in the plc0 register) m : 2, 4, 6, 8 (selected by bits plc02 to plc00 in the plc0 register) notes : 1. set the frequency divided by n between 2 mhz and 5 mhz. 2. set 10 mhz pll clock frequency 25 mhz divided by n (1) multiplied by m (2) rej09b0392-0064 rev.0.64 oct 12, 2007 page 84 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit bits plc05 and plc04 and bits plc02 to plc00 c an be set only once after reset. table 10.2 shows the example for setting pll clock frequencies. table 10.2 example for setting pll clock frequencies main clock setting value pll clock bits plc05 and plc04 bits plc02 to plc00 10 mhz 01b (divided by 2) 010b (multiplied by 4) 20 mhz 5 mhz 00b (not divided) 010b (multiplied by 4) 12 mhz 10b (divided by 4) 100b (multiplied by 8) 24 mhz 6 mhz 01b (divided by 2) 100b (multiplied by 8) rej09b0392-0064 rev.0.64 oct 12, 2007 page 85 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit figure 10.10 procedure to use pll clock as cpu clock source using the pll clock as the clock source for the cpu set the cm07 bit to 0 (main clock) set bits plc05 and plc04 (reference clock divided). set bits plc02 to plc 00 (multiplying factor) set the plc07 bit to 1 (pll operation) wait until the pll clock becomes stable (tsu(pll)) set the cm11 bit to 1 (pll cloc k for the cpu clock source) end rej09b0392-0064 rev.0.64 oct 12, 2007 page 86 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.2 cpu clock and peri pheral function clock two types of clock exists: cpu clock to operate the cpu peripheral function clocks to operate the peripheral functions. 10.2.1 cpu clock and bclk these are operating clocks for the cpu and watchdog timer. the main clock, sub clock, 125 khz on-chip oscillat or clock, or the pll clock can be selected as the clock source fo r the cpu clock. when the main clock, pll clock, or 125 khz on-chip oscillator clock is selected as the clock source for the cpu clock, the selected clock source can be divi ded by 1 (undivided), 2, 4, 8 or 16 to produce the cpu clock. use the cm06 bit in the cm0 register and bits cm17 and cm16 in the cm1 register to select a divide-by-n value. after reset, the 125 khz on-chip oscillator clock divided by 8 provides the cpu clock. during memory expansion or microprocessor mode , a bclk signal with the same frequency as the cpu clock can be output from the bclk pin by setting the pm07 bit in the pm0 register to 0 (output enabled). note that when entering stop mode or when the cm05 bit in the cm0 register is set to 1 (stop) in low- speed mode, the cm06 bit in the cm0 register is set to 1 (divide-by-8 mode). rej09b0392-0064 rev.0.64 oct 12, 2007 page 87 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.2.2 peripheral func tion clock (f1, fc32) these are operating clocks for the peripheral functions. f1 is produced from the main clock, the pll clock, or the 12 5 khz on-chip oscillator clock, and is used for timers a and b, uart0 to uart2, uart5 to uart7, si/o3, si/o4, and a/d converter. when the wait instruction is executed after setting the cm02 bit in the cm0 register to 1 (peripheral function clock f1 turned off during wait mode), or when the microcomputer is in low power consumption mode, the f1 clock is turned off. the fc32 clock is produced from the sub clock, and is used for timers a and b. this clock can be used when the sub clock is on. foco-s is used for timers a and b. foco-s can be used when the cm14 bit in the cm1 register is set to 0 (125 khz on-chip oscillator oscillates). figure 10.11 shows the peripheral function clock. figure 10.11 peripheral function clock 10.3 clock output function during single-chip mode, th e f8, f32, or fc clock can be output fr om the clkout pin. use bits cm01 and cm00 in the cm0 register to select. timer a, timer b fc fc32 1/32 foco-s foco-s f1 uart5 to uart7 si/o3, si/o4 uart0 to uart2 a/d converter main clock cm21 = 0 pll clock cm11 = 0 cm11 = 1 cm21 = 1 cm02 rej09b0392-0064 rev.0.64 oct 12, 2007 page 88 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.4 power control normal operating mode, wait mode, and stop mode are provided as the power consumption control. all mode states, except wait mode and stop mode, are called normal operating mode in this document. 10.4.1 normal operating mode normal operating mode is furthe r classified into seven modes. in normal operating mode, because the cpu clock and the peripheral function cl ocks both are on, the cpu and the peripheral functions are operating. power control is exercised by controlling the cpu clock frequency. the higher the cpu clock frequency, the greater the processing capability. the lower the cpu clock frequency, the smaller the power consum ption in the chip. if the unnecessary oscillator circuits are turned off, the power consumption is further reduced. before the clock sources for the cpu clock can be switched over, the new clock source to which switched must be oscillating stably. if the new clock source is the main clock, sub clock, or pll clock, allow a sufficient wait time in a prog ram until it becomes oscillating stably. when the cpu clock source is chang ed from the 125 khz on-chip osc illator to the main clock, change the operating mode to the medium speed mode (div ided by 8 mode) after the clock was divided by 8 (the cm06 bit in the cm0 register was set to 1) in the 125 khz on-chip oscillator mode. 10.4.1.1 high-speed mode the main clock divided by 1 provides the cpu clock. if the sub clock is on, fc32 can be used as the count source for timers a and b. 10.4.1.2 pll operating mode the pll clock serves as the cpu clock. if the sub cl ock is on, fc32 can be used as the count source for timers a and b. if fo co-s is oscillating, foco-s can be used as the count source for timers a and b. pll operating mode can be entered from high-speed mode or medium-speed mode. if pll oper- ating mode is to be changed to wait or stop m ode, first go to high-speed mode or medium-speed mode before changing. 10.4.1.3 medium-speed mode the main clock divided by 2, 4, 8, or 16 provides the cpu clock. if the sub clock is on, fc32 can be used as the count source for timers a and b. if foco-s is oscillating, foco-s can be used as the count source for timers a and b. 10.4.1.4 low-speed mode the sub clock provides the cpu cloc k. the main clock is used as the clock source for the peripheral function clock when the cm21 bit in the cm2 register is set to 0 (main clock or pll clock), and the 125 khz on-chip osci llator clock is used when t he cm21 bit is set to 1 (125 khz on-chip oscillator clock). the fc32 clock can be used as the count source for timers a and b. 10.4.1.5 low power consumption mode in this mode, the main clock is turned off afte r being placed in low speed mode. the sub clock pro- vides the cpu clock. the fc32 clock can be used as the count source for timers a and b. if foco-s is oscillating, foco-s can be used as the count s ource for timers a and b. simultaneously when this mode is selected, the cm 06 bit in the cm0 register becomes 1 (divided by 8 mode). in the low power consumption mode, do not change the cm06 bit. consequently, the medium-speed (divided by 8) mode is to be selected when the main clock is operated next. rej09b0392-0064 rev.0.64 oct 12, 2007 page 89 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.4.1.6 125 khz on-c hip oscillator mode the 125 khz on-chip o scillator clock divided by 1 (undivided), 2, 4, 8, or 16 prov ides the cpu clock. the 125 khz on-chip oscillato r clock is also the clock source for the peripheral function clocks. if the sub clock is on, fc32 can be used as the count s ource for timers a and b. when the operating mode is returned to the high- and medium-speed modes, set the cm06 bit in the cm0 register to 1 (divided by 8 mode). 10.4.1.7 125 khz on-chi p oscillator low po wer consumption mode the main clock is turned off after being placed in 125 khz on-chip oscilla tor mode. the cpu clock can be selected as in the 125 khz on-chip oscillator mode. the 125 kh z on-chip oscillator clock is the clock source for the peripheral function clocks. if th e sub clock is on, fc32 can be used as the count source for timers a and b. notes: 1. when the cm05 bit is set to 1 (main clock turn ed off) in low-speed mode, the mode goes to low power consumption mode and the cm06 bit is se t to 1 (divided by 8 mode) simultaneously. 2. the divide-by-n value can be selected the same way as in 125 khz on-chip oscillator mode. table 10.3 setting clock related bit and modes mode cm2 regis- ter cm1 register cm0 register cm21 cm11 cm14 cm17, cm16 cm07 cm06 cm05 cm04 pll operating mode divided by 10 1 - 00b 000- divided by 20 1 - 01b 000- divided by 40 1 - 10b 000- divided by 80 1 - - 010- divided by 160 1 - 11b 000- high-speed mode 0 0 - 00b 000- medium- speed mode divided by 20 0 - 01b 000- divided by 40 0 - 10b 000- divided by 80 0 - - 010- divided by 160 0 - 11b 000- low-speed mode - 0 - - 1 - 0 1 low power consumption mode 00-- 1 1 (1) 1 (1) 1 125 khz on-chip oscillator mode divided by 11 0 0 00b 000- divided by 21 0 0 01b 000- divided by 41 0 0 10b 000- divided by 81 0 0 - 010- divided by 161 0 0 11b 000- 125 khz on-chip oscillator low power consumption mode 1 0 0 (2) 0(2)1- - indicates that either 0 or 1 is set. rej09b0392-0064 rev.0.64 oct 12, 2007 page 90 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.4.2 wait mode in wait mode, the cpu clock is turned off, so are the cpu and the watchdog timer because they are operated by the cpu clock. however, if the cspro bit in the cspr register is 1 (count source protec- tion enabled), the watchdog timer remains active. be cause the main clock, sub clock, and 125 khz on- chip oscillator clock all are on , the peripheral functions using these clocks keep operating. 10.4.2.1 peripheral functi on clock stop function if the cm02 bit in the cm0 register is 1 (peripheral function clock f1 turned off during wait mode), the f1 clock is turned off while in wait mode, with the power consumption reduced that much. however, fc32 and foco-s (clock source of timers a and b) remain on for the cm02 bit. 10.4.2.2 entering wait mode the microcomputer is placed into wait mo de by executing the wait instruction. when the cm11 bit = 1 (cpu clock source is the pll clock), be sure to clear the cm11 bit in the cm1 register to 0 (cpu clock source is the main clock) before going to wait mode. the power consumption of the chip can be reduced by clearing the plc 07 bit in the plc0 register to 0 (pll stops). 10.4.2.3 pin status during wait mode table 10.4 lists pin status during wait mode. table 10.4 pin status during wait mode pin memory expansion mode microprocessor mode single-chip mode a0 to a19, d0 to d15, cs0 to cs3 , bhe retains status just prior to enter- ing wait mode cannot be used as a bus control pin rd , wr , wrl , wrh ?h? hlda , bclk ?h? ale ?l? i/o ports retains status just prior to enter- ing wait mode retains status before wait mode clkout when fc selected cannot be used as a clkout pin does not stop when f8, f32 selected does not stop when the cm02 bit is 0. when the cm02 bit is 1, the status immediately prior to entering wait mode is maintained rej09b0392-0064 rev.0.64 oct 12, 2007 page 91 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.4.2.4 exiting wait mode the microcomputer is moved out of wait mode by a hardware reset, nmi interrupt, low voltage detec- tion interrupt or peripheral function interrupt. if the microcomputer is to exit wait mode by a hardware reset, nmi interrupt, or lo w voltage detection interrupt, set the peripheral function interrupt bits ilvl2 to ilvl0 to 000b (interrupts disabled) before executing the wait instruction. the peripheral function interrupts are affected by the cm02 bit. if the cm02 bit is 0 (peripheral func- tion clocks not turned off during wa it mode), peripheral function interrupts can be used to exit wait mode. if the cm02 bit is 1 (per ipheral function clocks turned off during wait mode), the peripheral functions using the peripheral function clocks stop operating, so that only the peripheral functions activated by external signals can be used to exit wait mode. table 10.5 lists the resets and interrupts to exit wait mode and use conditions. if the microcomputer is to be moved out of wait m ode by a peripheral function interrupt, set up the fol- lowing before executing the wait instruction. (1) set bits ilvl2 to ilvl0 in the interrupt control register, for peripheral function interrupts used to exit wait mode. bits ilvl2 to ilvl0 in all other interrupt control registers, for peripheral function interrupts not used to exit wait mode, are set to 000b (interrupt disabled). (2) set the i flag to 1. (3) start operating the peripheral functions used to exit wait mode. when the peripheral function interrupt is used, an interrupt routine is performed after an interrupt request is generated and then the cpu clock is supplied again. when the microcomputer exits wait mode by the peri pheral function interrupt, the cpu clock is the same clock as the cpu clock ex ecuting the wait instruction. table 10.5 resets and interrupts to exit wait mode and use conditions reset, interrupt c m02 = 0 cm02 = 1 nmi interrupt usable usable serial interface interrupt usable when operating with internal or external clock usable when operating with exter- nal clock key input interrupt usable usable a/d conversion interrupt usable in one-shot mode or single sweep mode do not use timer a interrupt timer b interrupt usable in all modes usable in event counter mode or when the count source is fc32 int interrupt usable usable low voltage detection interrupt usable usable hardware reset 1 usable brown-out reset usable (see 6.1 brown-out reset ) watchdog timer reset usable when count sour ce protection mode is enabled (cspro = 1) rej09b0392-0064 rev.0.64 oct 12, 2007 page 92 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.4.3 stop mode in stop mode, all oscillator circuits are turned off, so are the cpu clock and the peripheral function clocks. therefore, the cpu and th e peripheral functions clocked by th ese clocks stop operating. the least amount of power is consumed in this mode. if the voltage applied to pins vcc1 and vcc2 is vram or greater, the internal ram is retained. when applying 2.7 or less voltage to pins vcc1 and vcc2, make sure vcc1 = vcc2 vram. however, the peripheral functions activated by external signals keep operating. the following resets and interrupts can be used to exit stop mode. table 10.6 lists resets and interrupts to stop mode and use conditions 10.4.3.1 entering stop mode the microcomputer is placed into stop mode by setti ng the cm10 bit in the cm1 register to 1 (all clocks turned off). at the same time, the cm06 bit in the cm0 register is set to 1 (divide-by-8 mode) and the cm15 bit in the cm1 register is set to 1 (main clock osci llator circuit driv e capability high). before entering stop mode, set the cm20 bit in the cm 2 register to 0 (oscillation stop, re-oscillation detection function disabled). also, if the cm11 bit in the cm1 register is 1 (pll clock for the cpu clock source), set the cm11 bit to 0 (main clock for the cpu clock source) and the plc07 bit in the plc0 register to 0 (pll turned off) before entering stop mode. 10.4.3.2 pin status in stop mode table 10.7 lists pin status in stop mode. table 10.6 resets and interrupts to stop mode and use conditions reset, interrupt condition nmi interrupt usable key input interrupt usable int interrupt usable timer a interrupt timer b interrupt usable when counting external pulses in event counter mode serial interface interrupt usable when external clock is selected low voltage detection interrupt usable (see 6.2 low voltage detection interrupt ) hardware reset 1 usable brown-out reset usable when digital filter is disabled (vw0c = 1) table 10.7 pin status in stop mode pin memory expansion mode microprocessor mode single-chip mode a0 to a19, d0 to d15, cs0 to cs3 , bhe retains status just prior to stop mode cannot be used as a bus control pin rd , wr , wrl , wrh ?h? hlda , bclk ?h? ale indeterminate i/o ports retains status just prior to stop mode retains status just prior to stop mode clkout cannot be used as a clkout pin ?h? rej09b0392-0064 rev.0.64 oct 12, 2007 page 93 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.4.3.3 exiting stop mode stop mode is exited by a hardware reset, nmi interrupt, low voltage detection interrupt, or peripheral function interrupt. when the hardware reset, nmi interrupt, or low voltage detection interrupt is used to exit stop mode, set bits ilvl2 to ilvl0 in the in terrupt control registers for the peripheral function interrupt to 000b (interrupt disabled) before setting the cm10 bit to 1. when the peripheral function interrupt is used to exit stop mode, set the cm10 bit to 1 after the fol- lowing settings are completed. (1) set bits ilvl2 to ilvl0 in the interrupt control registers to decide the peripheral priority level of the peripheral function interrupt. set the interrupt priority levels of the interrupts, not being used to exit stop mode, to 0 by setting bits ilvl2 to ilvl0 to 000b (interrupt disabled). (2) set the i flag to 1. (3) start operation of peripheral function being used to exit stop mode. when exiting stop mode by the peripheral function interrupt, the interrupt routine is performed after an interrupt request is generated and then the cpu clock is supplied again. when stop mode is exited by the peripheral func tion interrupt, low voltage detection interrupt, or nmi interrupt, the cpu clock so urce is as follows, in accordance with the cpu clock source setting before the microcomputer had entered stop mode. ? when the sub clock is the cpu clock before entering stop mode: sub clock ? when the main clock is the cpu clock source before entering stop mode: main clock divided by 8 ? when the 125 khz on-chip oscilla tor clock is the cpu clock sour ce before enterin g stop mode: 125 khz on-chip oscillator clock divided by 8 rej09b0392-0064 rev.0.64 oct 12, 2007 page 94 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit figure 10.12 shows the power control transition figure 10.12 power control transition cm10 = 1 all the oscillations stopped stop mode power control mode state transition reset wait mode 125 khz on-chip oscillator mode cm07 = 0, cm21 = 1 cm14 = 0, cm05 = 0 high-speed mode, medium-speed mode cm05 = 0 cm07 = 0 cm11 = 0 cm21 = 0 normal operation mode cm14 = 0 cm21 = 1 cm21 = 0 cpu operation stopped interrupt wait instruction interrupt cm04, cm05, cm06, cm07: bits in the cm0 register cm11, cm14, cm16, cm17: bits in the cm1 register cm21: bits in the cm2 register low-speed mode cm04 = 1, cm05 = 0, cm07 = 1 cm07 = 0 cm14 = 0 cm21 = 1 cm04 = 1 cm07 = 1 cm04 = 1 cm07 = 1 cm07 = 0 cm21 = 0 low power consumption mode cm04 = 1, cm05 = 1 cm07 = 1 125 khz on-chip osc illator low power consumption mode cm05 = 1, cm07 = 0 cm14 = 0, cm21 = 1 pll operation mode cm05 = 0 cm07 = 0 cm11 = 1 cm21 = 0 plc07 = 1 plc07 = 0 cm11 = 0 cm11 = 1 plc07 = 1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 95 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.5 system clock protection function the system clock protection function prohibits the cp u clock from changing clock sources when the main clock is selected as the cpu cloc k source. this is to prevent t he cpu clock from stopping by an unex- pected program operation. when the pm21 bit in the pm2 register is set to 1 (c lock change disabled), the following bits cannot be written to: ? bits cm02, cm05, and cm07 in the cm0 register ? bits cm10 and cm11 in the cm1 register ? the cm20 bit in the cm2 register ? all bits in the plc0 register when using the system clock protection function, set the cm05 bit in the cm0 register to 0 (main clock oscillation) and cm07 bit to 0 (main clock as cpu clock source ) and follow the procedure below. (1) set the prc1 bit in the prcr register to 1 (write to the pm2 register enabled). (2) set the pm21 bit in the pm2 register to 1 (clock change disabled). (3) set the prc1 bit in the prcr register to 0 (write to the pm2 register disabled). when the pm21 bit is set to 1, do not execute the wait instruction. rej09b0392-0064 rev.0.64 oct 12, 2007 page 96 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.6 oscillation stop and re-o scillation det ect function the oscillation stop and re-o scillation detect function is such that ma in clock oscillation circuit stop and re- oscillation are detected. at oscillati on stop or re-oscillation detection, re set oscillation stop or re-oscillation detection interrupt are generated. which is to be generated can be selected using the cm27 bit in the cm2 register. the oscillation stop and re-oscillation detect function ca n be enabled and disabled by the cm20 bit in the cm2 register. table 10.8 lists a spec ification overview of osc illation stop and re-oscilla- tion detect function. 10.6.1 operation when cm27 bit = 0 (oscillation stop detection reset) when main clock stop is detected when the cm20 bi t is 1 (oscillation stop, re -oscillation detection func- tion enabled), the microcom puter is initialized, coming to a ha lt (oscillation stop reset. refer to 4. ?spe- cial function registers (sfrs)?, 5. ?reset? ). this status is reset with hardware reset 1 or brown-out re set. also, even when re-o scillation is detected, the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage (dur- ing main clock stop, do not set the cm20 bit to 1 and the cm27 bit to 0). 10.6.2 operation when cm27 bit = 1 (osci llation stop and re-oscillation detect interrupt) when the main clock corresponds to the cpu cloc k source and the cm20 bi t is 1 (oscillation stop and re-oscillation detect function enabled), the system is placed in the following state if the main clock comes to a halt. ? oscillation stop and re-oscillation detect interrupt request occurs. ? cm14 bit = 0 (125 khz on-chi p oscillator clock oscillates) ? cm21 bit = 1 (125 khz on-chip o scillator clock for cpu cl ock source and clock source of peripheral function.) ? cm22 bit = 1 (main clock stop detected) ? cm23 bit = 1 (main clock stopped) when the pll clock corresponds to the cpu clock so urce and the cm20 bit is 1, the system is placed in the following state if the main clock comes to a halt. since the cm21 bit remains unchanged, set it to 1 (125 khz on-chip oscillator clo ck) inside the interrupt routine. ? oscillation stop and re-oscillation detect interrupt request occurs. ? cm14 bit = 0 (125 khz on-chi p oscillator clock oscillates) ? cm22 bit = 1 (main clock stop detected) ? cm23 bit = 1 (main clock stopped) ? cm21 bit remains unchanged when the cm20 bit is 1, the system is placed in the following state if the main clock re-oscillates from the stop condition. ? oscillation stop and re-oscillation detect interrupt request occurs. ? cm14 bit = 0 (125 khz on-chi p oscillator clock oscillates) ? cm22 bit = 1 (main clock re-oscillation detected) ? cm23 bit = 0 (main clock oscillation) ? cm21 bit remains unchanged table 10.8 specification overvi ew of oscillation stop and re-oscillation detect function item specification oscillation stop detectable clock and frequency bandwidth f(xin) 2 mhz enabling condition fo r oscillation stop, re-oscillation detect function set cm20 bit to 1 (enabled) operation at oscillation stop, re-oscillation detection reset occurs (when cm27 bit = 0) oscillation stop, re-oscillation detection interr upt generated (when cm27 bit = 1) rej09b0392-0064 rev.0.64 oct 12, 2007 page 97 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 10. clock generation circuit 10.6.3 how to use oscillation stop and re-oscillation detect function ? the oscillation stop and re-oscilla tion detect interrupt shares the vector with the watchdog timer interrupt and low voltage detection interrupt. if th e oscillation st op, re-oscillation detection and watchdog timer interrupts both are used, read the cm22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt. ? when the main clock re-o scillated after oscillation stop, the clock source for the cpu clock and peripheral functions must be switc hed to the main clock in a program. figure 10.13 shows the pro- cedure to switch clock so urce from 125 khz on-chip oscillator to main clock. ? simultaneously with osc illation stop and re-oscilla tion detection interrupt occurrence, the cm22 bit becomes 1. when the cm22 bit is se t to 1, oscillation stop and re-o scillation detection interrupt are disabled. by setting the cm22 bit to 0 in a pr ogram, oscillation stop and re-oscillation detection interrupt are enabled. ? if the main clock stops during lo w speed mode where the cm20 bit is 1, an oscillation stop and re- oscillation detection inte rrupt request is gen erated. at the same time, the 125 khz on-chip oscilla- tor starts oscillating. in this case, although the cpu clock is deri ved from the sub clock as it was before the interrupt occurred, the peripheral func tion clocks now are derived from the 125 khz on- chip oscillator clock. ? to enter wait mode while using the oscillation st op and re-oscillation detec tion function, set the cm02 bit to 0 (peripheral function clocks not turned off during wait mode). ? since the oscillation stop and re-oscillation det ection function is provided in preparation for main clock stop due to external factors, set the cm20 bit to 0 (oscillation stop and re-osc illation detection function disabled) where the main clock is stopped or oscillated in a program, that is where the stop mode is selected or the cm05 bit is altered. ? this function cannot be used if the main clock frequency is 2 mhz or less. in that case, set the cm20 bit to 0. figure 10.13 procedure to switch clock source fr om 125 khz on-chip oscillator to main clock switch the main clock bits cm21 to cm23: bits in the cm2 register yes end determine several times whether the cm23 bit is set to 0 (main clock oscillates) no set the cm06 bit to 1 (divide-by-8) set the cm22 bit to 0 (main clock stop, re-osci llation not detected) set the cm21 bit to 0 (main clock or pll clock) rej09b0392-0064 rev.0.64 oct 12, 2007 page 98 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 11. protection 11. protection in the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. figure 11.1 shows the prcr register. the following lists the registers protected by the prcr register. ? the prc0 bit protects registers cm0, cm1, cm2, plc0, and pclkr. ? the prc1 bit protects registers pm0, pm1, pm2, tb2sc, invc0, and invc1. ? the prc2 bit protects registers pd9, s3c, and s4c. ? the prc3 bit protects registers vcr2, d4int, and vw0c. ? the prc6 bit protects the prg2c register. set the prc2 bit to 1 (write enabled ) and then write to given sfr addres s, and the prc2 bit will be cleared to 0 (write protected). the registers protected by the prc2 bit should be changed in the next instruction after setting the prc2 bit to 1. make sure no interrupts or dma transfers will occur between the instruction in which the prc2 bit is set to 1 and the next instru ction. bits prc0, prc1, prc3, and prc6 are not auto- matically cleared to 0 by writin g to given sfr address. they can only be cleared in a program. figure 11.1 prcr register b7 0 0 0 b6 b5 b4 b1 b2 b3 protect register (1) symbol prcr address 000ah bit symbol bit name rw after reset 00h note : 1. the prc2 bit is set to 0 by writing to given sfr address after setting it to 1. other bits are not set to 0 automatically by the same token. therefore, set them to 0 in a program. b0 function ? (b5-b4) rw reserved bits set to 0 prc6 rw protect bit 6 enable write to the prg2c register 0 : write protected 1 : write enabled ? (b7) rw reserved bit set to 0 prc0 rw protect bit 0 enable write to registers cm0, cm1, cm2, plc0 and pclkr 0 : write protected 1 : write enabled prc1 rw protect bit 1 enable write to registers pm0, pm1, pm2, tb2sc, invc0, and invc1 0 : write protected 1 : write enabled prc2 rw protect bit 2 enable write to registers pd9, s3c, and s4c 0 : write protected 1 : write enabled prc3 rw protect bit 3 enable write to registers vcr2, d4int, and vw0c 0 : write protected 1 : write enabled rej09b0392-0064 rev.0.64 oct 12, 2007 page 99 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 12. interrupt 12. interrupt 12.1 type of interrupts figure 12.1 shows type of interrupts. figure 12.1 type of interrupts ? maskable interrupt : the interrupt priority can be changed by enabling (disabling) an inter- rupt with the interrupt enable flag (i flag) or by using interrupt priority levels. ? non-maskable interrupt : the interrupt priority cannot be changed by enabling (disabling) an interrupt with the interrupt enable flag (i flag) or by using interrupt prior- ity levels. interrupt software (non-maskable interrupt) hardware undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction special (non-maskable interrupt) peripheral function (1) (maskable interrupt) nmi dbc (2) watchdog timer oscillation stop and re-oscillation detection low voltage detection single step (2) address match notes : 1. the peripheral functions in the microcomputer are used to generate the peripheral interrupt. 2. do not normally use this interrupt because it is provided exclusively for use by development tools. rej09b0392-0064 rev.0.64 oct 12, 2007 page 100 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 12. interrupt 12.2 software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. 12.2.1 undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. 12.2.2 overflow interrupt an overflow interrupt occurs when executing the into instruction with the o flag in the flg register set to 1 (the operation resulted in an overflow). the followings are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, di v, divu, divx, neg, rmpa, sbb, sha, sub 12.2.3 brk interrupt a brk interrupt occurs when executing the brk instruction. 12.2.4 int instruction interrupt an int instruction interrupt occurs when executing the int instruction. software interrupt nos. 0 to 63 can be specified for the int instruction. because software interrupt nos. 2 to 31 and 41 to 51 are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function inter- rupts can be executed by ex ecuting the int instruction. in software interrupt nos. 0 to 31, the u flag is saved to the stack during instruction execution and is cleared to 0 (isp selected) before executing an inte rrupt sequence. the u flag is restored from the stack when returning from the interrupt routine. in so ftware interrupt nos. 32 to 63, the u flag does not change state during instruction execution, and the sp selected at the time is used. rej09b0392-0064 rev.0.64 oct 12, 2007 page 101 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 12. interrupt 12.3 hardware interrupts hardware interrupts are classified into two types: special interrupts and peripheral function interrupts. 12.3.1 special interrupts special interrupts are non-maskable interrupts. 12.3.1.1 nmi interrupt an nmi interrupt is generated when input on the nmi pin changes state from high to low. for details about the nmi interrupt, refer to 12.7 ? nmi interrupt? . 12.3.1.2 dbc interrupt do not normally use this interrup t because it is provided exclusiv ely for use by development tools. 12.3.1.3 watchdog timer interrupt generated by the watchdog timer. once a watchdog ti mer interrupt is generate d, be sure to initialize the watchdog timer. for details about the watchdog timer, refer to 13. ?watchdog timer? . 12.3.1.4 oscillation stop and re -oscillation det ection interrupt generated by the oscillation stop and re-oscillatio n detection function. for details about the oscilla- tion stop and re-oscillation detection function, refer to 10. ?clock generation circuit? . 12.3.1.5 low voltage detection interrupt generated by the voltage detection circuit. for detai ls about the voltage detection circuit, refer to 6. ?voltage detection circuit?. 12.3.1.6 single-step interrupt do not normally use this interrup t because it is provided exclusiv ely for use by development tools. 12.3.1.7 address match interrupt an address match interrupt is generated immediatel y before executing the in struction at the address indicated by registers rmad0 to rmad3 that correspond to one of the aier0 or aier1 bit in the aier register or the aier20 or ai er21 bit in the aier2 register which is 1 (address match interrupt enabled). for details about the ad dress match interr upt, refer to 12.9 ?address match interrupt? . 12.3.2 peripheral function interrupts the peripheral function interrupt occurs when a re quest from the peripheral functions in the microcom- puter is acknowledged. the peripheral function interrupt is a maskable interrupt. see tables 12.2 and 12.3 relocatable vector tables. refer to the descr iptions of each function for details about how the peripheral function interrupt occurs. rej09b0392-0064 rev.0.64 oct 12, 2007 page 102 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 12. interrupt 12.4 interrupts and interrupt vector one interrupt vector consists of 4 bytes. set the start address of each interrupt routine in the respective interrupt vectors. when an interrupt request is acc epted, the cpu branches to the address set in the cor- responding interrupt vector. figure 12.2 shows the interrupt vector. figure 12.2 interrupt vector 12.4.1 fixed vector tables the fixed vector tables are allocated to the addresses from fffdch to fffffh. table 12.1 lists the fixed vector table. in the flash memory version of microcomputer, the vector addresses (h) of fixed vectors are used by the id code check function. for details, refer to 22.2 ?functions to prevent flash memory from rewriting? . notes: 1. do not normally use this interrupt because it is provided exclusively for use by development tools. 2. if the contents of address fffe7h is ffh, program execution starts from the address shown by the vector in the relocatable vector table. table 12.1 fixed vector table interrupt source vector table addresses address (l) to address (h) reference undefined instruction (und instruction) fffdch to fffdfh m16c/60, m16c/20 series software manual overflow (into instruction) fffe0h to fffe3h brk instruction (2) fffe4h to fffe7h address match fffe8h to fffebh 12.9 ?address match interrupt? single step (1) fffech to fffefh - watchdog timer, oscillation stop and re-oscil- lation detection, low voltage detection ffff0h to ffff3h 13. ?watchdog timer? 10. ?clock generation circuit? 6. ?voltage detection circuit? dbc (1) ffff4h to ffff7h - nmi ffff8h to ffffbh 12.7 ? nmi interrupt? reset ffffch to fffffh 5. ?reset? middle-order address low-order address 0 0 0 0 high-order address 0 0 0 0 0 0 0 0 vector address (l) vector address (h) lsb msb rej09b0392-0064 rev.0.64 oct 12, 2007 page 103 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 12. interrupt 12.4.2 relocatable vector tables the 256 bytes beginning with the start address set in the intb register comprise a relocatable vector table area. tables 12.3 and 12.3 list the relocata ble vector tables. setting an even address in the intb register results in the interrupt sequence be ing executed faster than setting an odd address. notes: 1. address relative to address in intb. 2. use bits ifsr6 and ifsr7 in the ifsr register to select. 3. during i 2 c mode, interrupts nack and ack comprise the interrupt source. 4. use bits ifsr26 and ifsr27 in the ifsr2a register to select. 5. these interrupts cannot be disabled using the i flag. 6. bus collision detection: during ie mode, this bus collision detection constitu tes the interr upt source. during i 2 c mode, however, a start condition or a stop condition detection constitutes the interrupt source. table 12.2 relocatable vector table (1) interrupt source vector address (1) address (l) to address (h) software interrupt number reference brk instruction (5) +0 to +3 (0000h to 0003h) 0 m16c/60, m16c/20 series software manual ? (reserved) 1 int7 +8 to +11 (0008h to 000bh) 2 12.6 ? int interrupt? int6 +12 to +15 (000ch to 000fh) 3 int3 +16 to +19 (0010h to 0013h) 4 timer b5 +20 to +23 (0014h to 0017h) 5 15. ?timers? timer b4, uart1 bus collision detect (4, 6) +24 to +27 (0018h to 001bh) 6 15. ?timers? 17. ?serial interface? timer b3, uart0 bus collision detect (4, 6) +28 to +31 (001ch to 001fh) 7 si/o4, int5 (2) +32 to +35 (0020h to 0023h) 8 12.6 ? int interrupt? 17. ?serial interface? si/o3, int4 (2) +36 to +39 (0024h to 0027h) 9 uart2 bus collision detection (6) +40 to +43 (0028h to 002bh) 10 17. ?serial interface? dma0 +44 to +47 (002ch to 002fh) 11 14. ?dmac? dma1 +48 to +51 (0030h to 0033h) 12 key input interrupt +52 to +55 (0034h to 0037h) 13 12.8 ?key input interrupt? a/d +56 to +59 (0038h to 003bh) 14 18. ?a/d converter? uart2 transmit, nack2 (3) +60 to +63 (003ch to 003fh) 15 17. ?serial interface? uart2 receive, ack2 (3) +64 to +67 (0040h to 0043h) 16 uart0 transmit, nack0 (3) +68 to +71 (0044h to 0047h) 17 uart0 receive, ack0 (3) +72 to +75 (0048h to 004bh) 18 uart1 transmit, nack1 (3) +76 to +79 (004ch to 004fh) 19 uart1 receive, ack1 (3) +80 to +83 (0050h to 0053h) 20 timer a0 +84 to +87 (0054h to 0057h) 21 15. ?timers? timer a1 +88 to +91 (0058h to 005bh) 22 timer a2 +92 to +95 (005ch to 005fh) 23 timer a3 +96 to +99 (0060h to 0063h) 24 timer a4 +100 to +103 (0064h to 0067h) 25 timer b0 +104 to +107 (0068h to 006bh) 26 timer b1 +108 to +111 (006ch to 006fh) 27 timer b2 +112 to +115 (0070h to 0073h) 28 rej09b0392-0064 rev.0.64 oct 12, 2007 page 104 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 12. interrupt notes: 1. address relative to address in intb. 2. during i 2 c mode, interrupts nack and ack comprise the interrupt source. 3. these interrupts cannot be disabled using the i flag. 4. bus collision detection: during ie mode, this bus collisio n detection constitutes the factor of an inter- rupt. 5. bus collision detection: during ie mode, this bus collision detection constitu tes the interr upt source. during i 2 c mode, however, a start condition or a stop condition detection constitutes the interrupt source. table 12.3 relocatable vector table (2) interrupt source vector address (1) address (l) to address (h) software interrupt number reference int0 +116 to +119 (0074h to 0077h) 29 12.6 ? int interrupt? int1 +120 to +123 (0078h to 007bh) 30 int2 +124 to +127 (007ch to 007fh) 31 int instruction interrupt (3) +128 to +131 (0080h to 0083h) to +160 to +163 (00a0h to 00a3h) 32 to 40 m16c/60, m16c/20 series software manual dma2 +164 to +167 (00a4h to 00a7h) 41 14. ?dmac? dma3 +168 to +171(00a8h to 00abh) 42 uart5 bus collision detec- tion (4) +172 to +175(00ach to 0afh) 43 17. ?serial interface? uart5 transmit, nack5 (2) +176 to +179(00b0h to 00b3h) 44 uart5 receive, ack5 (2) +180 to +183(00b4h to 00b7h) 45 uart6 bus collision detec- tion (4) +184 to +187(00b8h to 00bbh) 46 uart6 transmit, nack6 (2) +188 to +191(00bch to 00bfh) 47 uart6 receive, ack6 (2) +192 to +195(00c0h to 00c3h) 48 uart7 bus collision detec- tion (4) +196 to +199(00c4h to 00c7h) 49 uart7 transmit, nack7 (2) +200 to +203(00c8h to 00cbh) 50 uart7 receive, ack7 (2) +204 to +207( 00cch to 00cfh) 51 - (reserved) 52 to 63 rej09b0392-0064 rev.0.64 oct 12, 2007 page 105 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 12. interrupt 12.5 interrupt control the following describes how to enabl e / disable the maskable interrupts, and how to set the priority in which order they are accepted. wh at is explained here does not apply to nonmaskable interrupts. use the i flag in the flg register, ipl, and bits il vl2 to ilvl0 in each interrupt control register to enable / disable the maskable interrupts. whether an in terrupt is requested or no t is indicated by the ir bit in each interrupt control register. figures 12.3 and 12.4 show the interrupt control registers. figure 12.3 interrupt control register (1) interrupt control register 1 (2) symbol tb5ic tb4ic / u1bcnic (3) tb3ic / u0bcnic (3) bcnic dm0ic to dm3ic kupic (4) adic s0tic to s2tic s0ric to s2ric ta0ic to ta4ic tb0ic to tb2ic u5bcnic to u7bcnic s5tic to s7tic s5ric to s7ric address 0045h 0046h 0047h 004ah 004bh, 004ch, 0069h, 006ah 004dh 004eh 0051h, 0053h, 004fh 0052h, 0054h, 0050h 0055h to 0059h 005ah to 005ch 006bh, 006eh, 0071h 006ch, 006fh, 0072h 006dh, 0070h, 0073h bit symbol bit name rw after reset xxxxx 000b xxxxx 000b xxxxx 000b xxxxx 000b xxxxx 000b xxxxx 000b xxxxx 000b xxxxx 000b xxxxx 000b xxxxx 000b xxxxx 000b xxxxx 000b xxxxx 000b xxxxx 000b function ir interrupt request bit 0: interrupt not requested 1: interrupt requested rw (1) notes : 1. the ir bit can only be reset by writing a 0. (do not write a 1). 2. to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. 3. use the ifsr2a register to select. 4. to use the key input interrupts, set the pcr7 bit in the pcr register to 0 (key input enabled). ? (b7-b4) no register bits. if necessary, set to 0. read as undefined value ? b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 interrupt priority level select bit ilvl0 rw ilvl1 ilvl2 rw rw b7 b6 b5 b4 b1 b2 b3 b0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 106 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 12. interrupt figure 12.4 interrupt control register (2) interrupt control register 2 (2) symbol int7ic (6,7) int6ic (6,7) int3ic (4) s4ic/int5ic (4) s3ic/int4ic (4) int0ic to int2ic address 0042h 0043h 0044h 0048h 0049h 005dh to 005fh bit symbol bit name rw after reset xx00x000b xx00x000b xx00x000b xx00x000b xx00x000b xx00x000b function ir interrupt request bit 0: interrupt not requested 1: interrupt requested pol polarity select bit (3, 5) 0 : select falling edge 1 : select rising edge rw (1) rw notes : 1. the ir bit can only be reset by writing a 0. (do not write a 1). 2. to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. 3. if the ifsri bit in the ifsr register are 1 (both edges), set the pol bit in the intiic register to 0 (falling edge) (i = 0 to 5). similarly, if bits ifsr30 and ifsr31 in the ifsr3a register are 1 (both edges), set the pol bits in registers int6ic and int7ic to 0 (falling edge). 4. when the byte pin is low and the processor mode is memory expansion or microprocessor mode, set bits ilvl2 to ilvl0 in registers int5ic to int3ic to 000b (interrupts disabled). 5. set the pol bit in the s3ic or s4ic register to 0 (falling edge) when the ifsr6 bit in the ifsr register = 0 (si/ o3 selected) or ifsr7 bit = 0 (si/o4 selected), respectively. 6. when the processor mode is memory expansion or micr oprocessor mode, set bits ilvl2 to ilvl0 in registers int6ic and int7ic to 000b (interrupts disabled). 7. to use the int6 interrupts, set the pcr5 bit in the pcr register to 0 (int6 input enabled). to use the int7 interrupts, set the pcr6 bit in the pcr register to 0 (int7 input enabled). ? (b5) reserved bit set to 0 rw ? (b7-b6) no register bits. if necessary, set to 0. read as undefined value ? b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 interrupt priority level select bit ilvl0 rw ilvl1 ilvl2 rw rw b7 b6 b5 b4 b1 b2 b3 b0 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 107 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 12. interrupt 12.5.1 i flag the i flag enables or disables the maskable inte rrupt. setting the i flag to 1 (enabled) enables the maskable interrupt. setting the i flag to 0 (disabled) disables all maskable interrupts. 12.5.2 ir bit the ir bit is set to 1 (interrupt requested) when an interrupt request is generated. then, when the inter- rupt request is accepted, the ir bit is cleared to 0 (interrupt not requested). the ir bit can be cleared to 0 in a program. do not write a 1 to this bit. 12.5.3 bits ilvl2 to ilvl0 and ipl interrupt priority leve ls can be set using bits ilvl2 to ilvl0. table 12.4 shows the settings of interrupt priori ty levels and table 12.5 shows the interrupt priority levels enabled by ipl. the followings are conditions under which an interrupt is accepted: ?i flag = 1 ? ir bit = 1 ? interrupt priority level > ipl the i flag, ir bit, bits ilvl2 to ilvl0 and ipl are independent each other. in no case do they affect one another. table 12.4 settings of interrupt priority levels bits ilvl2 to ilvl0 interrupt priority level priority order 000b level 0 (interrupt disabled) - 001b level 1 low 010b level 2 011b level 3 100b level 4 101b level 5 110b level 6 111b level 7 high table 12.5 interrupt priority levels enabled by ipl ipl enabled interrupt priority levels 000b interrupt levels 1 and above are enabled 001b interrupt levels 2 and above are enabled 010b interrupt levels 3 and above are enabled 011b interrupt levels 4 and above are enabled 100b interrupt levels 5 and above are enabled 101b interrupt levels 6 and above are enabled 110b interrupt levels 7 and above are enabled 111b all maskable interrupts are disabled rej09b0392-0064 rev.0.64 oct 12, 2007 page 108 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 12. interrupt 12.5.4 interrupt sequence an interrupt sequence ? what are performed over a period from the instant an interrupt request is accepted to the instant the interrupt routine is executed ? is described here. if an interrupt request occurs during execution of an in struction, the processor determines its priority when the execution of the instructio n is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execut ion of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. the cpu behavior during the interrupt sequence is described below. figure 12.5 shows time required for executing interrupt sequence. (1) the cpu obtains interrupt information (interrupt number and interrupt request level) by reading address 00000h. then, the ir bit applicable to the interrupt information is set to 0 (interrupt not requested). (2) the flg register, prior to an interrupt sequence, is saved to a temporary register (1) within the cpu. (3) flags i, d, and u in the flg register become as follows: ? the i flag is set to 0 (interrupt disabled) ? the d flag is set to 0 (single-step interrupt disabled) ? the u flag is set to 0 (isp selected) note that the u flag does not change states if an int instruction for software interrupt nos. 32 to 63 is executed. (4) the temporary register (1) within the cpu is saved to the stack. (5) the pc is saved to the stack. (6) the interrupt priority level of the acknowledged interrupt in ipl is set. (7) the start address of the relevant interrupt routin e set in the interrupt vector is stored in the pc. after the interrupt sequence is completed, an instru ction is executed from t he starting address of the interrupt routine. note: 1. temporary register cannot be modified by users. figure 12.5 time required for executing interrupt sequence 123456789 1011 address 00000h indeterminate (1) sp-2 sp-4 vec vec+2 indeterminate (1) sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information indeterminate (1) 12 13 14 15 16 17 18 pc cpu clock address bus data bus wr rd notes : 1. the indeterminate state depends on the instruction queue buffer. a read cycle occurs when the instruction queue buffer is ready to accept instructions. 2. the wr signal timing shown here is for the case where the stack is located in the internal ram. (2) rej09b0392-0064 rev.0.64 oct 12, 2007 page 109 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 12. interrupt 12.5.5 interrupt response time figure 12.6 shows the interrupt response time. the interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is gene rated till when the first in struction in the interrupt routine is executed. specifically, it consists of a ti me from when an interrupt request is generated till when the executing instruction is completed ((a) on figure 12.6) and a time during which the interrupt sequence is executed ((b) on figure 12.6). figure 12.6 interrupt response time 12.5.6 variation of ipl when in terrupt request is accepted when a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. when a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in table 12.6 is set in the ipl. table 12.6 li sts the ipl level that is set to ipl when a software or special interrupt is accepted. table 12.6 ipl level that is set to ipl when a software or special interrupt is accepted interrupt sources level set to ipl watchdog timer, nmi , oscillation stop and re -oscillation detection, low voltage detection 7 software, address match, dbc , single-step not changed instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) a time from when an interrupt request is generated till when the instruction at the time executing is completed. the length of this time varies with the instruction being executed. the divx instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) a time during which the interrupt sequence is executed. for details, see the table below. note, however, that the values in this table must be increased 2 cycles for the dbc interrupt and 1 cycle for the address match and single-step interrupts. sp value interrupt vector address 16-bit bus, without wait 8-bit bus, without wait even even odd odd even odd even odd 18 cycles 19 cycles 19 cycles 20 cycles 20 cycles 20 cycles 20 cycles 20 cycles rej09b0392-0064 rev.0.64 oct 12, 2007 page 110 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 12. interrupt 12.5.7 saving registers in the interrupt sequence, the flg register and pc are saved to the stack. at this time, the 4 high-order bits of the pc and t he 4 high-order (ipl) and 8 low-order bits in the flg register, 16 bits in total, are saved to the stack fi rst. next, the 16 low-order bits of the pc are saved. figure 12.7 shows the stack status before and after acceptance of interrupt request. the other necessary registers must be saved in a pr ogram at the beginning of the interrupt routine. use the pushm instruction, and all registers except sp can be saved with a single instruction. figure 12.7 stack status before and after acceptance of interrupt request the operation of saving registers carried out in the interrupt sequence is dependent on whether the sp (1), at the time of acceptance of an interrupt request, is even or odd. if the sp (1) is even, the flg reg- ister and the pc are saved, 16 bits at a time. if odd, they are saved in two steps, 8 bits at a time. figure 12.8 shows the operation of saving register. note: 1. when any int instruction in software numbers 32 to 63 has been executed, this is the sp indi- cated by the u flag. othe rwise, it is the isp. figure 12.8 operation of saving register address content of previous stack stack [sp] sp value before interrupt request is accepted. m m - 1 m - 2 m - 3 m - 4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m - 1 m - 2 m - 3 m - 4 address flgl content of previous stack stack flgh pch [sp] new sp value content of previous stack m + 1 msb lsb pcl pcm pcl : 8 low-order bits of pc pcm : 8 middle-order bits of pc pch : 4 high-order bits of pc flgl : 8 low-order bits of flg flgh : 4 high-order bits of flg (2) sp contains odd number [sp] (odd) [sp] - 1 (even) [sp] - 2 (odd) [sp] - 3 (even) [sp] - 4 (odd) [sp] - 5 (even) address sequence in which order registers are saved (2) (1) completed saving registers in four operations. (3) (4) (1) sp contains even number [sp] (even) [sp] - 1 (odd) [sp] - 2 (even) [sp] - 3 (odd) [sp] - 4 (even) [sp] - 5 (odd) note : 1. [sp] denotes the initial value of the sp when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address pcm stack flgl pcl sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits completed saving registers in two operations. pcm stack flgl pcl saved, 8 bits at a time flgh pch flgh pch pcl : 8 low-order bits of pc pcm : 8 middle-order bits of pc pch : 4 high-order bits of pc flgl : 8 low-order bits of flg flgh : 4 high-order bits of flg rej09b0392-0064 rev.0.64 oct 12, 2007 page 111 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 12. interrupt 12.5.8 returning from an interrupt routine the flg register and pc in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the reit instruction at the end of the interrupt rou- tine. thereafter the cpu returns to the program which was being executed before accepting the interrupt request. return the other registers saved by a program within the interrupt routine using the popm or similar instruction before executing the reit instruction. register bank is switched back to the bank used prio r to the interrupt sequence by the reit instruction. 12.5.9 interrupt priority if two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an interrupt request is generated or not), the inte rrupt with the highest priority is acknowledged. for maskable interrupts (peripheral functions interrupt), any desired priority level can be selected using bits ilvl2 to ilvl0. however, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. the watchdog timer and other special interrupts have their priority levels set in hardware. figure 12.9 shows the hardware interrupt priority. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. figure 12.9 hardware interrupt priority 12.5.10 interrupt priority level select circuit the interrupt priority level select circuit selects the highest priority interrupt in a sampled interrupt request(s) at the same sampling point. figure 12.10 shows the interr upts priority select circuit. reset watchdog timer oscillation stop and re-oscillation detection, low voltage detection peripheral function single step address match high low nmi dbc rej09b0392-0064 rev.0.64 oct 12, 2007 page 112 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 12. interrupt figure 12.10 interrupts priority select circuit interrupt request accepted level 0 (initial value) priority of peripheral function interrupts (if priority levels are same) interrupt request level determinate output to clock generating circuit (figure 10.1 clock generation circuit) i flag watchdog timer oscillation stop and re-oscillation detection dbc nmi address match low voltage detection higher lower uart6 receive, ack6 uart6 bus collision detection dma3 uart7 transmit, nack7 priority level of each interrupt uart5 transmit, nack5 uart7 receive, ack7 uart6 transmit, nack6 uart7 bus collision detection uart5 receive, ack5 timer b5 uart1 receive, ack1 timer b3, uart0 bus collision int1 timer b2 timer b0 timer a3 int0 timer b1 timer a4 dma2 int3 int2 timer a1 timer b4, uart1 bus collision timer a2 ipl priority level of each interrupt uart5 bus collision detection int6 int7 uart2 bus collision timer a0 uart1 transmit, nack1 uart0 transmit, nack0 uart2 transmit, nack2 key input interrupt dma0 si/o4, int5 si/o3, int4 dma1 a/d conversion uart0 receive, ack0 uart2 receive, ack2 rej09b0392-0064 rev.0.64 oct 12, 2007 page 113 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 12. interrupt 12.6 int interrupt inti interrupt (i = 0 to 7) is triggered by the edges of external inputs. the edge polarity is selected using the ifsri bit in the ifsr register, or the if sr30 or ifsr31 bit in the ifsr3a register. int4 and int5 share the interrupt vector and interrupt control register with si/o3 and si/o4, respectively. to use the int4 interrupt, set the ifsr6 bit in the ifsr register to 1 ( int4 ). to use the int5 interrupt, set the ifsr7 bit in the ifsr register to 1 ( int5 ). after modifying the ifsr6 or ifsr7 bit, clear the corres ponding ir bit to 0 (interrupt not requested) before enabling the interrupt. to use the int6 interrupt, set the pcr5 bit in the pcr register to 0 ( int6 input enabled). to use the int7 interrupt, set the pcr6 bit in the pcr register to 0 ( int7 input enabled). figure 12.11 shows the ifsr register, and figure 12.12 shows registers ifsr2a, ifsr3a, and pcr. figure 12.11 ifsr register b7 b6 b5 b4 b1 b2 b3 interrupt source select register symbol ifsr address 0207h bit symbol bit name rw after reset 00h b0 function ifsr0 rw 0 : one edge 1 : both edges (1) int0 interrupt polarity switch bit ifsr1 int1 interrupt polarity switch bit 0 : one edge 1 : both edges (1) ifsr2 int2 interrupt polarity switch bit 0 : one edge 1 : both edges (1) ifsr3 int3 interrupt polarity switch bit 0 : one edge 1 : both edges (1) ifsr4 int4 interrupt polarity switch bit 0 : one edge 1 : both edges (1) rw rw rw rw notes : 1. when setting this bit to 1 (both edges), make sure the pol bit in registers int0ic to int5ic are set to 0 (falling edge). 2. during memory expansion and microprocessor modes, when the data bus is 16 bits wide (byte pin is ?l?), set this bit to 0 (si/o3, si/o4). 3. when setting this bit to 0 (si/o3, si/o4), make sure the pol bit in registers s3ic and s4ic are set to 0 (falling edge). ifsr5 int5 interrupt polarity switch bit 0 : one edge 1 : both edges (1) rw ifsr6 interrupt request source select bit (2) 0 : si/o3 (3) 1 : int4 rw ifsr7 interrupt request source select bit (2) 0 : si/o4 (3) 1 : int5 rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 114 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 12. interrupt figure 12.12 registers ifsr2a, ifsr3a, and pcr b7 0 0 0 0 0 0 b6 b5 b4 b1 b2 b3 interrupt source select register 2 symbol ifsr2a address 0206h bit symbol bit name rw ? (b5-b0) after reset 00h b0 function reserved bits ifsr26 ifsr27 interrupt request source select bit (1) set to 0 rw rw rw 0 : timer b3 1 : uart0 bus collision detection interrupt request source select bit (2) 0 : timer b4 1 : uart1 bus collision detection notes : 1. timer b3 and uart0 bus collision detection share the vector and interrupt control register. when using timer b3 interrupt, clear the ifsr26 bit to 0 (timer b3). when using uart0 bus collision detection, set the ifsr26 bit to 1. 2. timer b4 and uart1 bus collision detection share the vector and interrupt control register. when using timer b4 interrupt, clear the ifsr27 bit to 0 (timer b4). when using uart1 bus collision detection, set the ifsr27 bit to 1. b7 b6 b5 b4 b1 b2 b3 port control register symbol pcr address 0366h bit symbol rw after reset 00000xx0b b0 notes : 1. to use the an2_4 pin as an analog input pin, set the pcr5 bit to 1 (int6 input disabled). 2. to use the an2_5 pin as an analog input pin, set the pcr6 bit to 1 (int7 input disabled). 3. to use pins an4 to an7 as analog input pins, set the pcr7 bit to 1 (key input disabled). bit name function pcr0 rw no register bits. if necessary, set to 0. read as 0 ? (b4-b1) ? pcr5 rw pcr6 rw pcr7 rw int6 input enable bit (1) int7 input enable bit (2) key input enable bit (3) 0 : enabled 1 : disabled 0 : enabled 1 : disabled 0 : enabled 1 : disabled port p1 control bit operation performed when the p1 register is read 0 : when the port is set for input, the input levels of pins p1_0 to p1_7 are read. when set for output, the port latch is read. 1 : the port latch is read regardless of whether the port is set for input or output. b7 0 0 0 0 0 0 b6 b5 b4 b1 b2 b3 interrupt source se lect register 3 symbol ifsr3a address 0205h bit symbol bit name rw ifsr30 after reset 00h b0 function ifsr31 ? (b7-b2) 0 : one edge 1 : both edges (1) rw rw rw 0 : one edge 1 : both edges (1) set to 0 note : 1. when setting this bit to 1 (both edges), make sure the pol bit in registers int6ic and int7ic are set to 0 (falling edge). int6 interrupt polarity switch bit int7 interrupt polarity switch bit reserved bits rej09b0392-0064 rev.0.64 oct 12, 2007 page 115 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 12. interrupt 12.7 nmi interrupt an nmi interrupt is generated when input on the nmi pin changes state from high to low. the nmi inter- rupt is a non-maskable interrupt. to use the nmi interrupt, set the pm24 bi t in the pm2 register to 1 ( nmi function). 12.8 key input interrupt of p10_4 to p10_7, a key input interrupt is generated when input on any of pins p10_4 to p10_7 which has had bits pd10_4 to pd10_7 in the pd10 register se t to 0 (input) goes low. key input interrupts can be used as a key-on wake up function, the function whic h gets the microcomputer out of wait or stop mode. however, if using the key input interrupt, do not us e p10_4 to p10_7 as analog input pins. figure 12.13 shows the block diagram of the key input interrupt. note, however, that while input on any pin which has had bits pd10_4 to pd10_7 set to 0 (input mode) is pulled low, inputs on all other pins of the port are not detected as interrupts. set the pcr7 bit in the pcr register to 0 (key input enabled) to use key input inter- rupts. figure 12.13 key input interrupt kupic register key input interrupt request pu25 bit in pur2 register pd10_7 bit in pd10 register pull-up transistor pull-up transistor pull-up transistor pull-up transistor pd10_7 bit in pd10 register pd10_6 bit in pd10 register pd10_5 bit in pd10 register pd10_4 bit in pd10 register ki3 ki2 ki1 ki0 interrupt control circuit rej09b0392-0064 rev.0.64 oct 12, 2007 page 116 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 12. interrupt 12.9 address match interrupt an address match interrupt is generated immediately be fore executing the instruction at the address indi- cated by the rmadi register (i = 0 to 3). set the st art address of any instruction in the rmadi register. use bits aier0 and aier1 in the aier register and bits aier20 and aier21 in the ai er2 register to enable or disable the interrupt. note that the addr ess match interrupt is unaffected by the i flag and ipl. when address match interrupt requests are acknowledged, the value of the pc that is saved to the stack area (refer to 12.5.7 ?saving registers? ) varies depending on the instruction at the address indicated by the rmadi register (the value of the pc that is saved to the stack area is not the correct return address.) therefore, follow one of the methods described below to return from the address match interrupt. ? rewrite the content of the stack and then use the reit instruction to return. ? restore the stack to its previous state before t he interrupt request was accepted by using the pop or similar other instruction and then use a jump instruction to return. table 12.7 shows the value of the pc that is saved to the stack area when an address match interrupt request is accepted. note that when using the external bus in 8 bits width, no address match interrupts can be used for external areas. figure 12.14 shows registers aier , aier2, and rmad0 to rmad3. note: value of the pc that is saved to the stack area: refer to 12.5.7 ?saving registers? . table 12.7 value of the pc that is saved to the stack area when an address match interrupt request is accepted instruction at the address indicated by th e rmadi register value of the pc that is saved to the stack area 16-bit op-code instruction instruction shown below among 8-bit operation code instructions add.b:s #imm8, dest sub.b:s #imm8, dest and.b:s #imm8, dest or.b:s #imm8, dest mov.b:s #i mm8, dest stz.b:s #imm8, dest stnz.b:s #imm8, dest stzx.b:s #imm81, #imm82,dest cmp.b:s #imm8, dest pushm src popm dest jmps #imm8 jsrs #imm8 mov.b:s #imm, dest (however, dest = a0 or a1) the address indicated by the rmadi register +2 instructions other than the above the address indicated by the rmadi register +1 table 12.8 relationship between address match interrupt sources and associated registers address match interrupt sources address match inte rrupt enable bit address match interrupt register address match interrupt 0 aier0 rmad0 address match interrupt 1 aier1 rmad1 address match interrupt 2 aier20 rmad2 address match interrupt 3 aier21 rmad3 rej09b0392-0064 rev.0.64 oct 12, 2007 page 117 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 12. interrupt figure 12.14 registers aier, aier2, and rmad0 to rmad3 b7 b6 b5 b4 b1 b2 b3 address match interrupt enable register symbol aier address 020eh bit symbol bit name rw aier0 after reset xxxxxx00b b0 function address match interrupt 0 enable bit aier1 ? (b7-b2) address match interrupt 1 enable bit 0 : interrupt disabled 1 : interrupt enabled no register bits. if necessary, set to 0. read as undefined value ? rw rw 0 : interrupt disabled 1 : interrupt enabled b7 b6 b5 b4 b1 b2 b3 address match interrupt enable register 2 symbol aier2 address 020fh bit symbol bit name rw aier20 after reset xxxxxx00b b0 function address match interrupt 2 enable bit aier21 ? (b7-b2) address match interrupt 3 enable bit 0 : interrupt disabled 1 : interrupt enabled no register bits. if necessary, set to 0. read as undefined value ? rw rw 0 : interrupt disabled 1 : interrupt enabled after reset address match interrupt register i (i = 0 to 3) symbol address setting range function rw address setting register for address match interrupt (b19 to b0) rw 00000h to fffffh no register bits. if necessary, set to 0. read as undefined value ? (b23) b7 b7 b0 rmad0 rmad1 rmad2 rmad3 0212h to 0210h 0216h to 0214h 021ah to 0218h 021eh to 021ch x00000h x00000h x00000h x00000h (b19) b3 (b16) b0 (b15) b7 (b8) b0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 118 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 13. watchdog timer 13. watchdog timer the watchdog timer detects whether the program is ou t of control. therefore, we recommend using the watchdog timer to improve reliabilit y of a system. the watchdog timer contains a 15-bit counter, and count source protection mode (enabled / disabled) is set here. table 13.1 shows the watchdog timer specification. refer to 5.4 ?watchdog timer reset? for details of watchdog timer reset. figure 13.1 shows the watchdog timer block diagram . figure 13.2 shows the registers wdtr, wdts, and wdc. figure 13.3 shows the cspr register and ofs1 address. figure 13.1 watchdog timer block diagram table 13.1 watchdog timer specification item when count source protection mode is disabled when count source protection mode is enabled count source cpu clock 125kh z on-chip oscillator clock count operation decrement count start condition either of the followings can be selected. count automatically starts after reset. count starts by writing to the wdts register. count stop condition stop mode, wait mode, hold state none watchdog timer reset condition reset write 00h, and then ffh to the wdtr register. underflow operation when the timer underflows watchdog timer interrupt or watchdog timer reset watchdog timer reset select function prescaler divide ratio set the wdc7 bit in the wdc re gister to select this mode. count source protection mode set the csproini bit (flash memory) in the ofs1 address to select whether this mode is enabled or disabled after reset. if this mode is set to disabled after reset, set the cspro bit (program) in the cspr register. start up or stop watchdog timer after reset set the wdton bit in the ofs1 address to select startup or stop. 1/128 1/2 watchdog timer write to wdtr register cm07 = 1 set to 7fffh (1) pm12 = 1 watchdog timer reset pm12 = 0 watchdog timer interrupt request prescaler cspro = 0 foco-s cspro = 1 cspro : bit in cspr register wdc7 : bit in wdc register pm12 : bit in pm1 register cm07 : bit in cm0 register note : 1. 0fffh is set when the cspro bit is set to 1 (count source protection mode enabled). internal reset signal (?l? active) 1/16 cm07 = 0, wdc7 = 0 cm07 = 0, wdc7 = 0 cpu clock hold rej09b0392-0064 rev.0.64 oct 12, 2007 page 119 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 13. watchdog timer figure 13.2 registers wdtr, wdts, and wdc b7 watchdog timer reset register symbol wdtr address 037dh rw after reset indeterminate b0 function setting 00h and then ffh initializes the watchdog timer. (1, 3) the watchdog timer is initialized to 7fffh when count source protection mode is disabled, and to 0fffh when count source protection mode is enabled. (2) wo notes : 1. make sure no interrupts or dma transfers will occur before writing ffh after writing 00h. 2. the watchdog timer is set to 0fffh when the cspro bit in the cspr register is set to 1 (count source protection mode enabled). 3. after the watchdog timer interrupt occurs, reset the watchdog timer by setting the wdtr register. b7 watchdog timer start register symbol wdts address 037eh rw after reset indeterminate b0 function the watchdog timer starts counting after a write instruction to this register wo b7 0 b6 b5 b4 b1 b2 b3 watchdog timer control register symbol wdc address 037fh bit symbol bit name rw ? (b4-b0) after reset 00xxxxxxb b0 function ? (b5) ? (b6) higher-order bits of watchdog timer wdc7 rw reserved bit prescaler select bit rw ? ro set to 0 0 : divided by 16 1 : divided by 128 no register bit. if necessary, set to 0. read as 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 120 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 13. watchdog timer figure 13.3 cspr register and ofs1 address count source prot ection mode register b7 0 0 0 0 0 0 0 b6 b5 b4 b1 b2 b3 symbol cspr address 037ch bit symbol bit name rw after reset (1) 00h b0 function cspro rw count source protection mode select bit (2) 0 : count source protection mode disabled 1 : count source protection mode enabled notes : 1. when a 0 is written to the csproini bit in the ofs1 address, 10000000b is set after reset. 2. write a 0 and then a 1 to set the cspro bit to 1. 0 cannot be set in a program. ? (b6-b0) rw reserved bits set to 0 optional feature select address (1) b7 1 1 1 1 1 b6 b5 b4 b1 b2 b3 symbol ofs1 address fffffh bit symbol bit name rw after reset ffh (2) b0 function notes : 1. the ofs1 address exists in flas h memory. set the values when writing a program. 2. the ofs1 address is set to ffh when a block including the ofs1 address is erased. 3. set the wdton bit to 0 (watchdog timer starts automatically after reset) when setting the csproini bit to 0 (count source protection mode enabled after reset). wdton watchdog timer start select bit (3) 0 : watchdog timer starts automatically after reset 1 : watchdog timer is in a stopped state after reset rw ? (b2-b1) rw reserved bits set to 1 romcp1 rw rom code protection bit 0 : rom code protection enabled 1 : rom code protection disabled ? (b6-b4) rw reserved bits set to 1 csproini rw after-reset count source protection mode select bit (3) 0 : count source protection mode enabled after reset 1 : count source protection mode disabled after reset rej09b0392-0064 rev.0.64 oct 12, 2007 page 121 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 13. watchdog timer 13.1 count source prot ection mode disabled the cpu clock is used for the watchdog timer count so urce when count source protection mode is dis- abled. table 13.2 lists the watchdog timer specifications (when count source protection mode is disabled). notes: 1. write 00h, and then ffh to the wdtr register to initialize the watchdog ti mer. the prescaler is ini- tialized after reset. some errors in the period of the watchdog timer may be caused by the prescaler. 2. the wdton bit cannot be changed by a program. wr ite a 0 to bit 0 of address fffffh with a flash programmer to set the wdton bit. table 13.2 watchdog timer specifications (when count source protection mode is disabled) item specification count source cpu clock count operation decrement period prescaler divide ratio (n) x watchdog timer count value (32768) (1) cpu clock n: 16 or 128 (selected by the wdc7 bit in the wdc register ) example: when cpu clock frequency = 16 mhz and prescaler divided by 16, period = approximately 32.8ms watchdog timer reset condition ? reset ? write 00h, and then ffh to the wdtr register. ? underflow count start condi- tion set the wdton bit (2) in the ofs1 address (fffffh) to select the watchdog timer operation after reset. ? when the wdton bit is set to 1 (watchdog timer is in stop state after reset) the watchdog timer and prescaler stop after reset and count starts by writing to the wdts register. ? when the wdton bit is set to 0 (watchdog timer starts automatically after reset) the watchdog timer and prescaler start counting automatically after reset. count stop condi- tion stop mode, wait mode, hold state (count resumes from the hold value after exiting.) operation when the timer underflows ? when the pm 12 bit in the pm1 register is set to 0 watchdog timer interrupt ? when the pm 12 bit in the pm1 register is set to 1 watchdog timer reset (see 5.4 ?watchdog timer reset? ) rej09b0392-0064 rev.0.64 oct 12, 2007 page 122 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 13. watchdog timer 13.2 count source prot ection mode enabled the 125 khz on-chip oscillato r clock is used for the wa tchdog timer count source when count source pro- tection mode is enabled. if the cpu clock stops when a program is out of contro l, the clock can still be supplied to the watchdog timer. table 13.3 lists the watchdog timer specifications (when count source protection mode is enabled). notes: 1. the wdton bit cannot be changed by a program. write 0 to bit 0 of address fffffh with a flash programmer to set the wdton bit. 2. even if 0 is written to the csproini bit in the ofs1 address, the cspro is set to 1. the csproini bit cannot be changed by a program. write 0 to bit 7 of address fffffh with a flash programmer to set the csproini bit. table 13.3 watchdog timer specifications (when count source protection mode is enabled) item specification count source 125 khz on-chip oscillator clock count operation decrement period watchdog timer count value (4096) 125 khz on-chip oscillator clock example: when 125 khz on-chip oscillator clock = 125 khz , period = approximately 32.8ms watchdog timer reset condition ? reset ? write 00h, and then ffh to the wdtr register. ? underflow count start condi- tion set the wdton bit (1) in the ofs1 address (fffffh) to select the watchdog timer operation after reset. ? when the wdton bit is set to 1 (watchdog timer is in stop state after reset) the watchdog timer and prescaler stop after reset and count starts by writing to the wdts register. ? when the wdton bit is set to 0 (watchdog timer starts automatically after reset) the watchdog timer and prescaler start counting automatically after reset. count stop condi- tion none (count does not stop in wait mode or in hold state once count starts. the mcu does not enter stop mode.) operation when the timer underflows watchdog timer reset (see 5.4 ?watchdog timer reset? ) registers, bits ? when the cspro bit in the cspr register is set to 1 (count source protection mode enabled) (2) , the followings are set automatically. -set 0fffh to the watchdog timer. -set the cm14 bit in the cm1 register to 0 (125 khz on-chip oscillator on). -set the pm12 bit in the pm1 register to 1 (the watchdog timer reset is generated when watchdog timer underflows.). ? the following conditions apply in count source protection mode. -writing to the cm10 bit in the cm1 register is disabled (it remains unchanged even if it is set to 1. the mcu does not enter stop mode.). -writing to the cm14 bit in the cm1 register is disabled (it remains unchanged even if it is set to 1. the 125 khz on-chip oscillator does not stop.). rej09b0392-0064 rev.0.64 oct 12, 2007 page 123 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 14. dmac 14. dmac the dmac (direct memory access cont roller) allows data to be transf erred without the cpu intervention. four dmac channels are included. each time a dma request occurs, the dmac transfers one (8 or 16-bit) data from the source address to the destination address. the dmac us es the same data bus as used by the cpu. because the dmac has higher priority of bus control than the cpu and because it makes use of a cycle steal method, it can transfer one word (16 bits) or on e byte (8 bits) of data within a very short time after a dma request is generated. figure 14.1 shows the dmac block diagram. t able 14.1 lists the dmac specifications. figures 14.2 to 14.5 show the dmac-related registers. figure 14.1 dmac block diagram a dma request is generated by a write to the dsr bit in the dmisl register (i = 0 to 3), as well as by an interrupt request which is generated by any function s pecified by bits dms and dsel4 to dsel0 in the dmisl register. however, unlike in the case of interrupt requests, dma requests are not affected by the i flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be accepted, dma requests are always accepted. furthermore, because the dmac does not affect interrupts, the ir bit in the interrupt control register does not change state due to a dma transfer. a data transfer is initiated each time a dma request is generated when the dmae bit in the dmicon regis- ter = 1 (dma enabled). however, if the cycle in whic h a dma request is generated is faster than the dma transfer cycle, the number of transfer requests generated and the number of times data is transferred may dma latch high-order bits dma latch low-order bits note : 1. pointer is incremented by a dma request. data bus low-order bits data bus high-order bits address bus dma2 source pointer sar2 (20) dma2 destination pointer dar2 (20) dma2 forward address pointer (20) (1) dma3 destination pointer dar3 (20) dma3 source pointer sar3 (20) dma3 forward address pointer (20) (1) (addresses 01a2h to 01a0h) (addresses 01a6h to 01a4h) (addresses 01b2h to 01b0h) (addresses 01b6h to 01b4h) dma0 source pointer sar0 (20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (1) dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (1) (addresses 0182h to 0180h) (addresses 0186h to 0184h) (addresses 0192h to 0190h) (addresses 0196h to 094h) dma2 transfer counter reload register tcr2 (16) dma2 transfer counter tcr2 (16) dma3 transfer counter reload register tcr3 (16) dma3 transfer counter tcr3 (16) (addresses 01a9h, 01a8h) (addresses 01b9h, 01b8h) dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) (addresses 0189h, 0188h) (addresses 0199h, 0198h) rej09b0392-0064 rev.0.64 oct 12, 2007 page 124 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 14. dmac not match. refer to 14.4 ?dma request? for details. notes: 1. dma transfer is not effective to any interrupt. dma transfer is affected neither by the i flag nor by the interrupt control register. 2. the selectable factors of dma requests differ with each channel. 3. make sure that no dmac-related registers (addre sses 0180h to 01bfh) are accessed by the dmac. i = 0 to 3 table 14.1 dmac specifications (3) item specification no. of channels 4 (cycle steal method) transfer memory space ? from given address in the 1-mbyte space to a fixed address ? from a fixed address to given address in the 1-mbyte space ? from a fixed address to a fixed address maximum no. of bytes transferred 128 kbytes (with 16-bit transfers) or 64 kbytes (with 8-bit transfers) dma request factors (1, 2) falling edge of int0 to int7 both edges of int0 to int7 timer a0 to timer a4 interrupt requests timer b0 to timer b5 interrupt requests uart0 to 2, uart5 to 7 transmission interrupt requests uart0 to 2, uart5 to 7 reception / ack interrupt requests si/o3, si/o4 interrupt requests a/d conversion interrupt requests software triggers channel priority dma0 > dma1 > dma2 > dma3 (dma0 takes precedence) transfer unit 8 bits or 16 bits transfer address direction forward or fixed (the so urce and destination addresses cannot both be in the forward direction.) transfer mode single transfer transfer is completed when the dmai transfer counter underflows. repeat transfer when the dmai transfer counter underflows, it is reloaded with the value of the dmai transfer counter reload register and a dma transfer is continued with it. dma interrupt request generation timing when the dmai transfer counter underflowed dma transfer start data transfer is initiated each time a dma request is generated when the dmae bit in the dmaicon register = 1 (enabled). dma trans- fer stop single transfer ? when the dmae bit is set to 0 (disabled) ? after the dmai transfer counter underflows repeat transfer when the dmae bit is set to 0 (disabled) reload timing for forward address pointer and dmai transfer counter when a data transfer is started after setting the dmae bit to 1 (enabled), the forward address pointer is reloaded wi th the value of the sari or dari pointer whichever is specified to be in the forward direction and the dmai transfer counter is reloaded with the value of the dmai transfer counter reload register. dma transfer cycles minimum 3 cycles between sfr and internal ram rej09b0392-0064 rev.0.64 oct 12, 2007 page 125 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 14. dmac figure 14.2 registers dm0sl, dm1sl, dm2sl, and dm3sl (1) b7 b6 b5 b4 b1 b2 b3 dmai source select r egister (i = 0 to 3) symbol dm0sl dm1sl dm2sl dm3sl address 0398h 039ah 0390h 0392h bit symbol rw after reset 00h 00h 00h 00h note : 1. the sources of dmai requests can be selected by a combination of the dms bit and bits dsel4 to dsel0 in the manner described in figure 14.3. b0 ? ? (b5) dms rw bit name function dsel0 dsel1 dsel2 dsel3 dsel4 dma request source select bit (note 1) rw rw rw rw dma request source expansion select bit 0: basic request source 1: extended request source no register bit. if necessary, set to 0. read as 0 dsr rw software dma request bit a dma request is generated by setting this bit to 1 when the dms bit is 0 (basic source) and bits dsel4 to dsel0 are 00001b (software trigger). read as 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 126 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 14. dmac figure 14.3 registers dm0sl, dm1sl, dm2sl, and dm3sl (2) dma0 dma2 dsel4 t o dsel0 dms = 0 (b as i c f ac t or o f r e qu es t) dms = 1 (ext en d e d f ac t or o f r e qu es t) dsel4 t o dsel0 dms = 0 (b as i c f ac t or o f r e qu es t) dms = 1 (ext en d e d f ac t or o f r e qu es t) 0 0 0 0 0 b f a lli n g e dg e o f int0 pi n - f a lli n g e dg e o f int2 pi n - s o ft ware t r igg er - s o ft ware t r igg er - 0 0 0 1 0 b ti mer a0 - ti mer a0 - 0 0 0 1 1 b ti mer a1 - ti mer a1 - 0 0 1 0 0 b ti mer a2 - ti mer a2 - 0 0 1 0 1 b ti mer a3 - ti mer a3 - 0 0 1 1 0 b ti mer a4 b o th e dg es o f int0 pi n ti mer a4 b o th e dg es o f int2 pi n 0 0 1 1 1 b ti mer b0 ti mer b3 ti mer b0 ti mer b3 0 1 0 0 0 b ti mer b1 ti mer b4 ti mer b1 ti mer b4 0 1 0 0 1 b ti mer b2 ti mer b5 ti mer b2 ti mer b5 0 1 0 1 0 b uart0 t ransm i ss i on - uart0 t ransm i ss i on - 0 1 0 1 1 b uart0 rece pti on - uart0 rece pti on - 0 1 1 0 0 b uart2 t ransm i ss i on - uart2 t ransm i ss i on - 0 1 1 0 1 b uart2 rece pti on - uart2 rece pti on - 0 1 1 1 0 b a/d con v ers i on - a/d con v ers i on - 0 1 1 1 1 b uart1 t ransm i ss i on - uart1 t ransm i ss i on - 1 0 0 0 0 b uart1 rece pti on f a lli n g e dg e o f int4 pi n uart1 rece pti on f a lli n g e dg e o f int6 pi n 1 0 0 0 1 b uart5 t ransm i ss i on b o th e dg es o f int4 pi n uart5 t ransm i ss i on b o th e dg es o f int6 pi n 1 0 0 1 0 b uart5 rece pti on - uart5 rece pti on - 1 0 0 1 1 b uart6 t ransm i ss i on - uart6 t ransm i ss i on - 1 0 1 0 0 b uart6 rece pti on - uart6 rece pti on - 1 0 1 0 1 b uart7 t ransm i ss i on - uart7 t ransm i ss i on - 1 0 1 1 0 b uart7 rece pti on - uart7 rece pti on - 1 0 1 1 1 b - --- 1 1 x x x b -- -- x i n di ca t es 0 or 1. - i n di ca t es no se tti n g. x i n di ca t es 0 or 1. - i n di ca t es no se tti n g. dma1 dma3 dsel4 t o dsel0 dms = 0 (b as i c f ac t or o f r e qu es t) dms = 1 (ext en d e d f ac t or o f r e qu es t) dsel4 t o dsel0 dms = 0 (b as i c f ac t or o f r e qu es t) dms = 1 (ext en d e d f ac t or o f r e qu es t) f a lli n g e dg e o f int1 pi n - f a lli n g e dg e o f int3 pi n - s o ft ware t r igg er - s o ft ware t r igg er - ti mer a0 - ti mer a0 - ti mer a1 - ti mer a1 - ti mer a2 - ti mer a2 - ti mer a3 si / o3 ti mer a3 si / o3 ti mer a4 si / o4 ti mer a4 si / o4 ti mer b0 b o th e dg es o f int1 pi n ti mer b0 b o th e dg es o f int3 pi n ti mer b1 - ti mer b1 - ti mer b2 - ti mer b2 - uart0 t ransm i ss i on - uart0 t ransm i ss i on - uart0 rece pti on / ack0 - uart0 rece pti on / ack0 - uart2 t ransm i ss i on - uart2 t ransm i ss i on - uart2 rece pti on / ack2 - uart2 rece pti on / ack2 - a/d con v ers i on - a/d con v ers i on - uart1 rece pti on / ack1 - uart1 rece pti on / ack1 - uart1 t ransm i ss i on f a lli n g e dg e o f int5 pi n uart1 t ransm i ss i on f a lli n g e dg e o f int7 pi n uart5 t ransm i ss i on b o th e dg es o f int5 pi n uart5 t ransm i ss i on b o th e dg es o f int7 pi n uart5 rece pti on / ack5 - uart5 rece pti on / ack5 - uart6 t ransm i ss i on - uart6 t ransm i ss i on - uart6 rece pti on / ack6 - uart6 rece pti on / ack6 - uart7 t ransm i ss i on - uart7 t ransm i ss i on - uart7 rece pti on / ack7 - uart7 rece pti on / ack7 - - -- - - -- - x i n di ca t es 0 or 1. - i n di ca t es no se tti n g. x i n di ca t es 0 or 1. - i n di ca t es no se tti n g. 0 0 0 0 1 b 0 0 0 0 0 b 0 0 0 1 0 b 0 0 0 1 1 b 0 0 1 0 0 b 0 0 1 0 1 b 0 0 1 1 0 b 0 0 1 1 1 b 0 1 0 0 0 b 0 1 0 0 1 b 0 1 0 1 0 b 0 1 0 1 1 b 0 1 1 0 0 b 0 1 1 0 1 b 0 1 1 1 0 b 0 1 1 1 1 b 1 0 0 0 0 b 1 0 0 0 1 b 1 0 0 1 0 b 1 0 0 1 1 b 1 0 1 0 0 b 1 0 1 0 1 b 1 0 1 1 0 b 1 0 1 1 1 b 1 1 x x x b 0 0 0 0 1 b 0 0 0 0 0 b 0 0 0 1 0 b 0 0 0 1 1 b 0 0 1 0 0 b 0 0 1 0 1 b 0 0 1 1 0 b 0 0 1 1 1 b 0 1 0 0 0 b 0 1 0 0 1 b 0 1 0 1 0 b 0 1 0 1 1 b 0 1 1 0 0 b 0 1 1 0 1 b 0 1 1 1 0 b 0 1 1 1 1 b 1 0 0 0 0 b 1 0 0 0 1 b 1 0 0 1 0 b 1 0 0 1 1 b 1 0 1 0 0 b 1 0 1 0 1 b 1 0 1 1 0 b 1 0 1 1 1 b 1 1 x x x b 0 0 0 0 1 b 0 0 0 0 0 b 0 0 0 1 0 b 0 0 0 1 1 b 0 0 1 0 0 b 0 0 1 0 1 b 0 0 1 1 0 b 0 0 1 1 1 b 0 1 0 0 0 b 0 1 0 0 1 b 0 1 0 1 0 b 0 1 0 1 1 b 0 1 1 0 0 b 0 1 1 0 1 b 0 1 1 1 0 b 0 1 1 1 1 b 1 0 0 0 0 b 1 0 0 0 1 b 1 0 0 1 0 b 1 0 0 1 1 b 1 0 1 0 0 b 1 0 1 0 1 b 1 0 1 1 0 b 1 0 1 1 1 b 1 1 x x x b 0 0 0 0 1 b rej09b0392-0064 rev.0.64 oct 12, 2007 page 127 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 14. dmac figure 14.4 registers dm0con, dm1con, dm2con, and dm3con dmai control regist er (i = 0 to 3) symbol dm0con dm1con dm2con dm3con address bit symbol rw dmbit after reset notes : 1. the dmas bit can be set to 0 by writing a 0 in a program (this bit remains unchanged even if 1 is written). 2. set at least either the dad bit or dsd bit to 0 (address direction fixed). dmasl dmas dmae dsd rw rw (1) rw rw dad rw ? (b7-b6) ? rw b7 b6 b5 b4 b1 b2 b3 b0 bit name no register bits. if necessary, set to 0. read as 0 dma request bit dma enable bit function 0 : dma not requested 1 : dma requested 0 : disabled 1 : enabled 018ch 019ch 01ach 01bch 00000x00b 00000x00b 00000x00b 00000x00b repeat transfer mode select bit 0 : single transfer 1 : repeat transfer transfer unit bit select bit 0 : 16 bits 1 : 8 bits source address direction select bit (2) 0 : fixed 1 : forward destination address direction select bit (2) 0 : fixed 1 : forward rej09b0392-0064 rev.0.64 oct 12, 2007 page 128 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 14. dmac figure 14.5 registers sar0, sar1 , sar2, sar3, dar0, dar1, d ar2, dar3, tcr0, tcr1, tcr2, and tcr3 after reset dmai source pointer (i = 0 to 3) (1) symbol address setting range function rw set the source address of transfer rw 00000h to fffffh no register bits. if necessary, set to 0. read as 0 ? (b23) b7 b7 b0 sar0 sar1 sar2 sar3 0182h to 0180h 0192h to 0190h 01a2h to 01a0h 01b2h to 01b0h 0xxxxxh 0xxxxxh 0xxxxxh 0xxxxxh (b19) b3 (b16) b0 (b15) b7 (b8) b0 note : 1. if the dsd bit in the dmicon register is 0 (fixed), write to this register when the dmae bit in the dmicon register is 0 (dma disabled). if the dsd bit is 1 (forward direction), this register can be written to at any time. if the dsd bit is 1 and the dmae bit is 1 (dma enabled), the dmai forward address pointer can be read from this register. otherwise, the value written to it can be read. after reset dmai destination pointer (i = 0 to 3) (1) symbol address setting range function rw set the destination address of transfer rw 00000h to fffffh no register bits. if necessary, set to 0. read as 0 ? (b23) b7 b7 b0 dar0 dar1 dar2 dar3 0186h to 0184h 0196h to 0194h 01a6h to 01a4h 01b6h to 01b4h 0xxxxxh 0xxxxxh 0xxxxxh 0xxxxxh (b19) b3 (b16) b0 (b15) b7 (b8) b0 note : 1. if the dad bit in the dmicon register is 0 (fixed), write to this register when the dmae bit in the dmicon register is 0 (dma disabled). if the dad bit is 1 (forward direction), this register can be written to at any time. if the dad bit is 1 and the dmae bit is 1 (dma enabled), the dmai forward address pointer can be read from this register. otherwise, the value written to it can be read. after reset dmai transfer counter (i = 0 to 3) symbol address setting range rw tcr0 tcr1 tcr2 tcr3 0189h to 0188h 0199h to 0198h 01a9h to 01a8h 01b9h to 01b8h indeterminate indeterminate indeterminate indeterminate b7 b0 (b15) b7 (b8) b0 rw 0000h to ffffh set the transfer count minus 1. the written value is stored in the dmai transfer counter reload register, and when the dmae bit in the dmicon register is set to 1 (dma enabled) or the dmai transfer counter underflows when the dmasl bit in the dmicon register is 1 (repeat transfer), the value of the dmai transfer counter reload register is transferred to the dmai transfer counter. when read, the dmai transfer counter is read. function rej09b0392-0064 rev.0.64 oct 12, 2007 page 129 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 14. dmac 14.1 transfer cycles transfer cycle is composed of a bus cycle to read data from source address (source read) and a bus cycle to write data to destination address (destination wr ite). the number of read and write bus cycles depends on source and destination addresses. during memory extension and microprocessor modes, it is also affected by the byte pin level. furthermore, the bus cycle itself is extended by a software wait or rdy signal. 14.1.1 effect of source and destination addresses when a 16-bit data is transferred with a 16-bit data bus and a source address starts with an odd address, source-read cycle is incremented by one bus cycle, compared to a source address starting with an even address. when a 16-bit data is transferred with a 16-bit dat a bus and a destination address starts with an odd address, destination-write cycle is incremented by one bus cycle, co mpared to a destination address starting with an even address. 14.1.2 effect of byte pin level during memory extension and microprocessor modes, if 16 bits of data are to be transferred on an 8-bit data bus (input on the byte pin = high), the operatio n is accomplished by transferring 8 bits of data twice. therefore, this operation requires two bus cy cles to read data and two bus cycles to write data. furthermore, if the dmac is to access the internal area (internal rom, internal ram, or sfr), unlike in the case of the cpu, the dmac does it throug h the data bus width selected by the byte pin. 14.1.3 effect of software wait for memory or sfr accesses in which one or more software wait states are inserted, the number of bus cycles required for that access increases by an amount equal to software wait states. 14.1.4 effect of rdy signal during memory extension and microprocessor modes, dma transfers to and from an external area are affected by the rdy signal. refer to 8.2.6 ? rdy signal? . figure 14.6 shows the example of the transfer cycles for source read. for co nvenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating tr ansfer cycles, take into consideration each condi- tion for the source read a nd the destination write cycle, respective ly. for example, when data is trans- ferred in 16 bit units using an 8-bit bus ((2) on figure 14.6), two source read bus cycles and two destination write bus cycles are required. rej09b0392-0064 rev.0.64 oct 12, 2007 page 130 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 14. dmac figure 14.6 transfer cycles for source read bclk address bus rd signal wr signal data bus cpu use cpu use source dummy cycle bclk address bus rd signal wr signal data bus cpu use cpu use source dummy cycle source + 1 note : 1. the same timing changes occur with the respective conditions at the destination as at the source. bclk address bus rd signal wr signal data bus cpu use cpu use source dummy cycle source + 1 bclk address bus rd signal wr signal data bus cpu use cpu use source dummy cycle destination destination destination destination (1) when the transfer unit is 8 or 16 bits and the source of transfer is an even address (4) when the source read cycle under cond ition (2) has one wa it state inserted (2) when the transfer unit is 16 bits and the source address of transfer is an odd address, or when the transfer unit is 16 bits and an 8-bit bus is used (3) when the source read cycle under cond ition (1) has one wa it state inserted cpu use cpu use source destination dummy cycle cpu use cpu use source destination dummy cycle source + 1 cpu use cpu use source dummy cycle destination cpu use cpu use source dummy cycle source + 1 destination rej09b0392-0064 rev.0.64 oct 12, 2007 page 131 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 14. dmac 14.2 dma transfer cycles the number of dma transfer cycles can be calculated as follows. table 14.2 lists the dmac transfer cycles. table 14.3 lists the coefficients j and k. number of transfer cycles per transfer unit = number of read cycles j + number of write cycles k - indicates that no condition exists. notes: 1. it depends on the set value of the cse register. 2. it depends on the set value of the pm20 bit in the pm2 register. table 14.2 dmac transfer cycles transfer unit bus width access address single-chip mode memory expansion mode microprocessor mode no. of read cycles no. of write cycles no. of read cycles no. of write cycles 8-bit transfers (dmbit= 1) 16-bit (byte = ?l?) even1111 odd1111 8-bit (byte = ?h?) even - - 1 1 odd - - 1 1 16-bit transfers (dmbit= 0) 16-bit (byte = ?l?) even1111 odd2222 8-bit (byte = ?h?) even - - 2 2 odd - - 2 2 table 14.3 coefficients j and k internal area external area internal rom, ram sfr separate bus multiplex bus no wait with wait 1-wait (2) 2-wait (2) no wait with wait (1) with wait (1) 1-wait 2-wait 3-wait 1-wait 2-wait 3-wait j12231234334 k12232234334 rej09b0392-0064 rev.0.64 oct 12, 2007 page 132 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 14. dmac 14.3 dma enabled when a data transfer starts after setting the dmae bit in the dmicon register (i = 0 to 3) to 1 (enabled), the dmac operates as follows: (1) reload the forward address pointer with the sari register value when the dsd bit in the dmicon register is 1 (forward) or the dari register valu e when the dad bit in the dmicon register is 1 (forward). (2) reload the dmai transfer co unter with the dmai transfer co unter reload register value. if the dmae bit is set to 1 again while it remains se t, the dmac performs the above operation. however, if a dma request may occur simultaneously when the dmae bit is being written, follow the steps below. step 1: write 1 to the dmae bit and dmas bit in the dmicon register simultaneously. step 2: make sure that the dmai is in an initia l state as described above (1) and (2) in a program. if the dmai is not in an initial state, the above steps should be repeated. 14.4 dma request the dmac can generate a dma request as triggered by the factor of request t hat is selected with the dms bit and bits dsel4 to dsel0 in the dmisl register (i = 0 to 3) on either channel. table 14.1 lists the timing at which the dmas bit changes state. whenever a dma request is generated, the dmas bit is set to 1 (dma requested) regardless of whether or not the dmae bit is set. if the dmae bit is set to 1 (enabled) when this occurs, the dmas bit is set to 0 (dma not requested) immediately before a data transfer starts. this bit cannot be set to 1 in a program (it can only be set to 0). the dmas bit may be set to 1 when the dms bit or bits dsel4 to dsel0 change state. therefore, always be sure to set the dmas bit to 0 after changing the dms bit or bits dsel4 to dsel0. because if the dmae bit is 1, a data transfer starts immediately after a dma request is generated, the dmas bit in almost all cases is 0 when read in a program. read the dmae bit to determine whether the dmac is enabled. i = 0 to 3 table 14.4 timing at which the dmas bit changes state dma factor dmas bit in the dmicon register timing at which the bit is set to 1 t iming at which the bit is set to 0 software trigger when the dsr bit in the dmisl register is set to 1 ? immediately before a data transfer starts ? when set by writing a 0 in a program peripheral function when the interrupt control register for the peripheral function that is selected by bits dsel4 to dsel0 and dms in the dmisl register has its ir bit set to 1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 133 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 14. dmac 14.5 channel priority and dma transfer timing if several channels of dma0 to dma3 are enabled and dma transfer request signals are detected active in the same sampling period (one period from a falling edge to th e next falling edge of bclk), the dmas bit on each channel is set to 1 (dma requested) at the same time. in this case, the dma requests are arbitrated according to the channel priority: dma0 > dma1 > dma2 > dma3. the following describes dmac operation when dma0 and dma1 requests are detected active in the same sampling period. fig- ure 14.7 shows an example of dma transfer by external factors. in figure 14.7, dma0 request having priority is re ceived first to start a transfer when dma0 and dma1 requests are generated simultaneously. after one dma0 tr ansfer is completed, a bus access privilege is returned to the cpu. when the cpu has completed one bus access, a dma1 transfer starts. after one dma1 transfer is completed, the bus access privilege is again returned to the cpu. in addition, dma requests cannot be incremented since each channel has one dmas bit. therefore, when dma requests, as dma1 in figure 14.7, occurs more than one time, the dmas bit is set to 0 after getting the bus access privilege. the bus access privilege is returned to the cpu when one transfer is completed. refer to 8.2.7 ? hold signal? for details about bus access privilege. figure 14.7 dma transfer by external factors bclk dma0 dma1 dmas bit in dma0 dmas bit in dma1 cpu int0 int1 bus access privilege an example when dma requests for ex ternal factors are detected active at the same time and dma transfer is executed in the shortest cycle rej09b0392-0064 rev.0.64 oct 12, 2007 page 134 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 15. timers 15. timers eleven 16-bit timers, each capable of operating indep endently of the others, can be classified by function as either timer a (five) and timer b (six). the count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. figure 15. 1 shows timers a and b count source, and figures 15.2 and 15.3 show block diagrams of timer a and timer b configuration, respectively. figure 15.1 timers a and b count source 1/32 fc32 set the cpsr bit in the cpsrf register to 1 (prescaler reset). reset f1timab or f2timab f8timab f32timab f1 f2timab pclk0 = 0 pclk0 = 1 main clock generation circuit or pll frequency synthesizer subclock generation circuit 1/2 f64timab foco-s foco-s foco-s cm21 = 0 fc32 fc cm21 = 1 1/2 1/8 1/4 clock generation circuit 125 khz on-chip oscillator cm21 : bit in the cm2 register pclk0 : bit in the pclkr register f1timab rej09b0392-0064 rev.0.64 oct 12, 2007 page 135 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 15. timers figure 15.2 timer a configuration tmod1 to tmod0 00 11 10 01 ta4tgh to ta4tgl tmod1 to tmod0 00 11 10 01 ta3tgh to ta3tgl tmod1 to tmod0 00 11 10 01 ta2tgh to ta2tgl tmod1 to tmod0 00 11 10 01 ta1tgh to ta1tgl 00: timer mode 10: one-shot timer mode 11: pwm mode 01: event counter mode 01: event counter mode 01: event counter mode 01: event counter mode 01: event counter mode ta0in (1) ta1in ta2in ta3in ta4in timer a0 timer a1 timer a2 timer a3 timer a4 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt noise filter noise filter noise filter noise filter noise filter timer b2 overflow or underflow note: 1. be aware that ta0in shares pins with tb5in. 00: timer mode 10: one-shot timer mode 11: pwm mode 00: timer mode 10: one-shot timer mode 11: pwm mode 00: timer mode 10: one-shot timer mode 11: pwm mode 00: timer mode 10: one-shot timer mode 11: pwm mode tmod1 to tmod0 00 11 10 01 ta0tgh to ta0tgl tck1 to tck0, tmod1 to tmod0 : bits in the taimr register taigh to taigl : bits in the on sf register or trgsr register tcs0 to tcs7 : bits in registers tacs0 to tacs2 i = 0 to 4 tck1 to tck0 00 01 10 11 000 001 010 110 tcs2 to tcs0 011 101 tck1 to tck0 00 01 10 11 000 001 010 110 tcs6 to tcs4 011 101 tcs7 tck1 to tck0 00 01 10 11 000 001 010 110 tcs2 to tcs0 011 101 tcs3 tck1 to tck0 00 01 10 11 000 001 010 110 tcs6 to tcs4 011 101 tcs7 tck1 to tck0 00 01 10 11 000 001 010 110 tcs2 to tcs0 011 101 tcs3 tcs3 1 0 1 0 1 0 1 0 1 0 fc32 foco-s f64timab f32timab f8timab f1timab or f2timab rej09b0392-0064 rev.0.64 oct 12, 2007 page 136 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 15. timers figure 15.3 timer b configuration tmod1 to tmod0 1 0 tck1 tmod1 to tmod0 1 0 tck1 tmod1 to tmod0 1 0 tck1 tmod1 to tmod0 1 0 tck1 tmod1 to tmod0 1 0 tck1 tmod1 to tmod0 1 0 tck1 tb0in timer b0 timer b0 interrupt noise filter tb1in timer b1 timer b1 interrupt noise filter noise filter tb2in timer b2 timer b2 interrupt tb3in timer b3 timer b3 interrupt noise filter tb4in timer b4 timer b4 interrupt noise filter tb5in (1) timer b5 timer b5 interrupt noise filter note: 1. be aware that tb5in shares pins with ta0in. timer b2 overflow or underflow (to a count source of timer a) 01: event counter mode 00: timer mode 10: pulse width / pulse period measurement mode 01: event counter mode 01: event counter mode 01: event counter mode 01: event counter mode 01: event counter mode 00: timer mode 10: pulse width / pulse period measurement mode 00: timer mode 10: pulse width / pulse period measurement mode 00: timer mode 10: pulse width / pulse period measurement mode 00: timer mode 10: pulse width / pulse period measurement mode 00: timer mode 10: pulse width / pulse period measurement mode tck1 to tck0, tmod1 to tmod0 : bits in the tbimr register (i = 0 to 5) tcs0 to tcs7 : bits in registers tbcs0 to tbcs3 tck1 to tck0 00 01 10 11 000 001 010 110 tcs2 to tcs0 011 101 tck1 to tck0 00 01 10 11 000 001 010 110 tcs6 to tcs4 011 101 tck1 to tck0 00 01 10 11 000 001 010 110 tcs2 to tcs0 011 101 tck1 to tck0 00 01 10 11 000 001 010 110 tcs2 to tcs0 011 101 tck1 to tck0 00 01 10 11 000 001 010 110 tcs6 to tcs4 011 101 tck1 to tck0 00 01 10 11 000 001 010 110 tcs2 to tcs0 011 101 tcs3 tcs7 tcs3 tcs3 tcs7 tcs3 1 0 1 0 1 0 1 0 1 0 1 0 fc32 foco-s f64timab f32timab f8timab f1timab or f2timab rej09b0392-0064 rev.0.64 oct 12, 2007 page 137 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 15. timers 15.1 timer a figure 15.4 shows a timer a block diagram. figures 15.5 to 15.9 show registers related to timer a. timer a supports the following four modes. except in event counter mode, timers a0 to a4 all have the same function. use bits tmod1 to tmod0 in the taimr register (i = 0 to 4) to select the desired mode. ? timer mode the timer counts an internal count source. ? event counter mode the timer counts pulses from an external device or overflows and underflows of other timers. ? one-shot timer mode the timer outputs a pulse only once before it reaches the minimum count 0000h. ? pulse width modulation (pwm) mode the timer outputs pulses in a given width successively. figure 15.4 timer a block diagram increment / decrement reload register timer (gate function): tmod1 to tmod0 = 00, mr2 = 1 timer: tmod1 to tmod0 = 00, mr2 = 0 one-shot timer: tmod1 to tmod0 = 10 pulse width modulation: tmod1 to tmod0 = 11 taiin tb2 overflow (1) count source select taj overflow (1) tais mro toggle flip flop taiout decrement taiud tak overflow (1) polarity select notes: 1. overflow or underflow 01 taitgh to taitgl mr2 0 1 tmod1 to tmod0 00 10 11 01 tck1 to tck0, tmod1 to tmod0, mr2 to mr1 : bits in the taimr register taitgh to taitgl : bits in the onsf register when i=0, bits in the trgsr register when i = 1 to 4 tais : bits in the tabsr register taiud : bits in the udf register tcs0 to tcs7 : bits in the registers tacs0 to tacs2 pofsi : bits in the tapofs register event counter: tmod1 to tmod0 = 01 00 10 11 tmod1 to tmod0, mr2 to external trigger circuit data bus 0 1 pofsi tck1 to tck0 00 01 10 11 000 001 010 110 or tcs6 to tcs4 tcs2 to tcs0 011 101 tcs3 or tcs7 always decrement except in event counter mode 1 0 i = 0 to 4 j = i - 1, however, j = 4 if i = 0 k = i + 1, however, k = 0 if i = 4 tai taj tak timer a0 timer a4 timer a1 timer a1 timer a0 timer a2 timer a2 timer a1 timer a3 timer a3 timer a2 timer a4 timer a4 timer a3 timer a0 fc32 foco-s f64timab f32timab f8timab f1timab or f2timab counter rej09b0392-0064 rev.0.64 oct 12, 2007 page 138 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 15. timers figure 15.5 registers ta0mr to ta4mr and ta0 to ta4 b7 b6 b5 b4 b1 b2 b3 symbol ta0mr to ta4mr address 0336h to 033ah after reset 00h b0 function bit symbol bit name rw timer ai mode register (i= 0 to 4) note : 1. valid when the bit3 or the bit 7 in registers tacs0 to tacs2 is set to 0 (tck0, tck1 enabled). function varies with each operation mode mr1 rw mr2 rw mr3 rw tck1 rw count source select bit (1) (function varies with each operation mode) tck0 rw mr0 rw b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode operation mode select bit tmod1 tmod0 rw rw (b15) (b8) b7 symbol ta0 ta1 ta2 ta3 ta4 address 0327h to 0326h 0329h to 0328h 032bh to 032ah 032dh to 032ch 032fh to 032eh after reset indeterminate indeterminate indeterminate indeterminate indeterminate b0 setting range mode function rw timer ai register (i= 0 to 4) (1) 0000h to ffffh divide the count source by n + 1 where n = set value timer mode rw wo 0000h to ffffh (2, 4) divide the count source by n where n = set value, and the counter stops one-shot timer mode notes : 1. access to the register in 16-bit units. 2. if the tai register is set to 0000h, the counter does not work and timer ai interrupt requests are not generated either. furthermore, if pulse output is selected, no pulses are output from the taiout pin. 3. if the tai register is set to 0000h, the pulse width modulator does not work, the output level on the taiout pin remains low, and timer ai interrupt requests are not generated either. the same applies when the 8 high-order bits of the timer tai register are set to 00h while operating as an 8-bit pulse width modulator. 4. use the mov instruction to write to the tai register. 5. the timer counts pulses from an external device or overflows or underflows in other timers. rw 0000h to ffffh divide the count source by ffffh ? n + 1 where n = set value when counting up or by n + 1 when counting down (5) event counter mode pulse width modulation mode (16-bit pwm) modify the pulse width as follows: pwm period: (2 16 ? 1) / fj pwm pulse width: n / fj where n = set value, fj = count source frequency 0000h to fffeh (3, 4) wo pulse width modulation mode (8-bit pwm) modify the pulse width as follows: pwm period: (2 8 ? 1) (m + 1) / fj pwm pulse width: (m + 1)n / fj where n = high-order address set value, m = low-order address set value, fj = count source frequency 00h to feh (high-order address) 00h to ffh (low-order address) (3, 4) wo b7 b0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 139 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 15. timers figure 15.6 registers tabsr and udf b7 b6 b5 b4 b1 b2 b3 symbol tabsr address 0320h after reset 00h b0 function bit symbol bit name rw count start flag 0 : stop counting 1 : start counting tb0s tb2s timer a3 count start flag timer b2 count start flag rw rw rw rw ta4s rw ta3s timer b0 count start flag timer b1 count start flag tb1s timer a4 count start flag timer a1 count start flag ta1s rw timer a2 count start flag rw ta2s timer a0 count start flag ta0s rw b7 b6 b5 b4 b1 b2 b3 symbol udf address 0324h after reset 00h b0 function bit symbol bit name rw up / down flag notes : 1. set the port direction bits for pins ta2in to ta4in and pins ta2out to ta4out to 0 (input mode). 2. when not using the two-phase pulse signal proce ssing function, set the bit corresponding to timer a2 to timer a4 to 0. rw 0 : decrement 1 : increment enabled during event counter mode (when not using two-phase pulse signal) timer a0 up / down flag rw ta1ud ta0ud ta3ud ta2ud ta4ud 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled (1, 2) rw rw rw timer a1 up / down flag timer a2 up / down flag timer a3 up / down flag timer a4 up / down flag rw ta2p timer a2 two-phase pulse signal processing select bit rw ta3p timer a3 two-phase pulse signal processing select bit rw ta4p timer a4 two-phase pulse signal processing select bit rej09b0392-0064 rev.0.64 oct 12, 2007 page 140 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 15. timers figure 15.7 registers onsf and trgsr b7 b6 b5 b4 b1 b2 b3 symbol onsf address 0322h after reset 00h b0 function bit symbol bit name rw tazie ta0tgh rw rw rw z-phase input enable bit timer a0 event / trigger select bit ta0tgl one-shot start flag 0 : z-phase input disabled 1 : z-phase input enabled b7 b6 0 0 : input on ta0in pin is selected (1) 0 1 : tb2 is selected (2) 1 0 : ta4 is selected (2) 1 1 : ta1 is selected (2) notes : 1. make sure the pd7_1 bit in the pd7 register is set to 0 ( input mode). 2. overflow or underflow. timer a3 one-shot start flag rw rw ta4os ta3os timer a4 one-shot start flag timer a1 one-shot start flag ta1os rw timer a2 one-shot start flag rw ta2os the timer starts counting by setting this bit to 1 while bits tmod1 and tmod0 in the taimr register (i = 0 to 4) = 10b (one-shot timer mode) and the mr2 bit in the taimr register = 0 (taios bit enabled). read as 0 timer a0 one-shot start flag ta0os rw b7 b6 b5 b4 b1 b2 b3 symbol trgsr address 0323h after reset 00h b0 function bit symbol bit name rw trigger select register notes : 1. set the port direction bits for the pins ta1in to ta4in to 0 (input mode). 2. overflow or underflow b1 b0 0 0 : input on ta1in is selected (1) 0 1 : tb2 is selected (2) 1 0 : ta0 is selected (2) 1 1 : ta2 is selected (2) timer a1 event / trigger select bit rw rw ta1tgh ta1tgl b3 b2 0 0 : input on ta2in is selected (1) 0 1 : tb2 is selected (2) 1 0 : ta1 is selected (2) 1 1 : ta3 is selected (2) timer a2 event / trigger select bit rw rw ta2tgh ta2tgl b5 b4 0 0 : input on ta3in is selected (1) 0 1 : tb2 is selected (2) 1 0 : ta2 is selected (2) 1 1 : ta4 is selected (2) timer a3 event / trigger select bit rw rw ta3tgh ta3tgl b7 b6 0 0 : input on ta4in is selected (1) 0 1 : tb2 is selected (2) 1 0 : ta3 is selected (2) 1 1 : ta0 is selected (2) timer a4 event / trigger select bit rw rw ta4tgh ta4tgl rej09b0392-0064 rev.0.64 oct 12, 2007 page 141 of 373 under development preliminary specification specification in this preliminary version is subject to change. m16c/64 group 15. timers figure 15.8 registers cpsrf, tacs0, and tacs1 clock prescaler reset flag b7 b6 b5 b4 b1 b2 b3 symbol cpsrf address 0015h bit symbol bit name rw after reset 0xxxxxxxb b0 function ? (b6-b0) ? no register bits. if necessary, set to 0. read as undefined value cpsr rw clock prescaler reset flag initializing the clock prescaler. (read as 0) b7 b6 b5 b4 b1 b2 b3 symbol tacs0 to tacs1 address 01d0h to 01d1h after reset 00h b0 function bit symbol bit name rw timer a count source select register 0, timer a count source select register 1 b2 b1 b0 0 0 0 : f1timab or f2timab (1) 0 0 1 : f8timab 0 1 0 : f32timab 0 1 1 : f64timab 1 0 0 : do not set 1 0 1 : foco-s 1 1 0 : f c32 1 1 1 : do not set tai count source select bit tacs0 register: i = 0, j = 1 tacs1 register: i = 2, j = 3 note : 1. set this value at the pclk0 bit in the pclkr register. tcs1 tcs2 tcs0 rw rw rw taj count source select bit b6 b5 b4 0 0 0 : f1timab or f2timab (1) 0 0 1 : f8timab 0 1 0 : f32timab 0 1 1 : f64timab 1 0 0 : do not set 1 0 1 : foco-s 1 1 0 : fc32 1 1 1 : do not set tcs5 rw rw tcs4 rw tcs6 rw tcs3 1 : tck0, tck1 enabled, tcs0 to tcs2 disabled 0 : tck0, tck1 disabled, tcs0 to tcs2 enabled tai count source option specified bit tcs7 rw 1 : tck0, tck1 enabled, tcs4 to tcs6 disabled 0 : tck0, tck1 disabled, tcs4 to tcs6 enabled taj count source option specified bit rej09b0392-0064 rev.0.64 oct 12, 2007 page 142 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.9 registers tacs2 and tapofs b7 b6 b5 b4 b1 b2 b3 symbol tacs2 address 01d2h after reset x0h b0 timer a count source select register 2 note : 1. set this value at the pclk0 bit in the pclkr register. function bit symbol bit name rw b2 b1 b0 0 0 0 : f1timab or f2timab (1) 0 0 1 : f8timab 0 1 0 : f32timab 0 1 1 : f64timab 1 0 0 : do not set 1 0 1 : foco-s 1 1 0 : fc32 1 1 1 : do not set ta4 count source select bit tcs1 tcs2 tcs0 rw rw rw ? ? (b7-b4) no register bits. if necessary, set to 0. read as undefined value. rw tcs3 1 : tck0, tck1 enabled, tcs0 to tcs2 disabled 0 : tck0, tck1 disabled, tcs0 to tcs2 enabled ta4 count source option specified bit b7 b6 b5 b4 b1 b2 b3 symbol tapofs address 01d5h after reset xxx00000b b0 function bit symbol bit name rw no register bits. if necessary, set to 0. read as undefined value timer a waveform output function select register ta3out output polar control bit rw rw pofs4 pofs3 ta4out output polar control bit ta1out output polar control bit pofs1 rw ta2out output polar control bit rw pofs2 0 : output waveform "h" active 1 : output waveform "h" active (output reversed) ta0out output polar control bit pofs0 rw ? (b7-b5) ? rej09b0392-0064 rev.0.64 oct 12, 2007 page 143 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers 15.1.1 timer mode in timer mode, the timer counts a c ount source generated internally (see table 15.1 ). figure 15.10 shows taimr register in timer mode. i = 0 to 4 figure 15.10 taimr register in timer mode table 15.1 specifications in timer mode item specification count source f1timab, f2timab, f8timab, f32timab, f64timab, foco-s, fc32 count operation ? decrement ? when the timer underflows, it reloads the rel oad register contents and continues counting divide ratio 1 / (n+1) n: set value of tai register 0000h to ffffh count start condition set the tais bit in the tabsr register to 1 (start counting) count stop condition set the tais bit to 0 (stop counting) interrupt request generation timing timer underflow taiin pin function i/o port or gate input taiout pin function i/o port or pulse output read from timer count value can be read by reading the tai register write to timer ? when not counting value written to the tai register is written to both reload register and counter ? when counting value written to the tai register is written to only reload register (transferred to counter when reloaded next) select function ? gate function counting can be started and stopped by an input signal to the taiin pin ? pulse output function whenever the timer underflows, the output polarity of taiout pin is inverted. when the tais bit is set to 0 (stop counting), the pin outputs ?l.? ? output polarity control while the output polarity of the taiout pin is inverted (the tais bit is set to 0 (stop counting)), the pin outputs ?h.? b7 0 0 0 b6 b5 b4 b1 b2 b3 symbol ta0mr to ta4mr address 0336h to 033ah after reset 00h b0 function bit symbol bit name rw timer ai mode register (i = 0 to 4) notes : 1. the ta0out pin is n-channel open drain output. 2. set the port direction bit for the taiin pin to 0 (input mode). 3. selected by the pclk0 bit in the pclkr register. 4. valid when the tcs3 bit or tcs7 bit in registers tacs0 to tacs2 is set to 0 (tck0, tck1 enabled). rw b1 b0 0 0 : timer mode operation mode select bit rw tmod1 tmod0 tck0 mr3 rw set to 0 in timer mode tck1 rw count source select bit (4) b1 b0 0 0 : f1timab or f2timab (3) 0 1 : f8timab 1 0 : f32timab 1 1 : fc32 pulse output function select bit rw mr0 0 : no pulse output (taiout pin functions as i/o port) 1 : pulse output (1) (taiout pin functions as a pulse output pin) gate function select bit b4 b3 0 0 : gate function not available 0 1 : (taiin pin functions as i/o port) 1 0 : counts while input on the taiin pin is low (2) 1 1 : counts while input on the taiin pin is high (2) rw mr1 rw mr2 rej09b0392-0064 rev.0.64 oct 12, 2007 page 144 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers 15.1.2 event counter mode in event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. timers a2, a3, and a4 can count two-phase external signals. table 15.2 lists specifica- tions in event counter mode (when not processing two-phase pulse signal). figure 15.11 shows the taimr register in event counter mode (when not using two-phase pulse signal processing). i = 0 to 4 table 15.2 specifications in event counter mode (when not processing two-phase pulse signal) item specification count source ? external signals input to the taiin pin (effective edge can be selected in a program) ? timer b2 overflows or underflows, timer aj (j = i - 1, except j = 4 if i = 0) overflows or underflows, timer ak (k = i + 1, except k=0 if i = 4) overflows or underflows count operation ? increment or decr ement can be selected by program. ? when the timer overflows or underflows, it reloads the reload register con- tents and continues counting. when operating in free-running mode, the timer continues counting without reloading. divide ratio ? 1/ (ffffh - n + 1) for increment ? 1/ (n + 1) fo r decrement n: set value of the tai register 0000h to ffffh count start condition set the tais bit in the tabsr register to 1 (start counting) count stop condition set the tais bit to 0 (stop counting) interrupt request genera- tion timing timer overflow or underflow taiin pin function i/o port or count source input taiout pin function i/o port, pulse output read from timer count value can be read by reading the tai register write to timer ? when not counting value written to the tai register is written to both reload register and counter ? when counting value written to the tai register is written to only reload register (transferred to counter when reloaded next) select function ? free-run count function even when the timer overflows or underf lows, the reload register content is not reloaded to it ? pulse output function whenever the timer underflows or underflow s, the output polarity of the taiout pin is inverted. when the tais bit is set to 0 (stop counting), the pin outputs low. ? output polarity control while the output polarity of the taiout pin is inverted (the tais bit is set to 0 (stop counting)), the pin outputs high. rej09b0392-0064 rev.0.64 oct 12, 2007 page 145 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.11 taimr register in event counter mode (when not using two-phase pulse signal processing) b7 1 0 0 0 b6 b5 b4 b1 b2 b3 symbol ta0mr to ta4mr address 0336h to 033ah after reset 00h b0 function bit symbol bit name rw timer ai mode regist er (i = 0 to 4) (when not using two-phase pulse signal processing) notes : 1. during event counter mode, the count source can be selected using registers onsf and trgsr. 2. valid when bits taitgh and taitgl in the onsf or trgsr register are 00b (taiin pin input). 3. the ta0out pin is n-channel open drain output. rw mr1 count polarity select bit (2) 0 : counts falling edge of external signal 1 : counts rising edge of external signal rw tck0 count operation type select bit 0 : reload type 1 : free-run type rw b1 b0 0 1 : event counter mode (1) operation mode select bit rw tmod1 tmod0 mr2 rw write 0 in event counter mode mr3 rw write 0 in event counter mode tck1 rw can be 0 or 1 when not using two-phase pulse signal processing pulse output function select bit rw mr0 0 : pulse is not output (taiout pin functions as i/o port) 1 : pulse is output (3) (taiout pin functions as pulse output pin) rej09b0392-0064 rev.0.64 oct 12, 2007 page 146 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers table 15.3 lists specifications in event counter mode (when processing two-phase pulse signal with timers a2, a3, and a4). figure 15.12 shows registers ta2mr to ta4mr in event counter mode (when using two-phase pulse signal processing with timers a2, a3, and a4). i = 2 to 4, j = 2, 3, k = 3, 4 note: 1. only timer a3 is selectable. timer a2 is fixed to normal processing operati on, and timer a4 is fixed to multiply-by-4 processing operation. table 15.3 specifications in event counter mode (when processing two-phase pulse signal with timers a2, a3, and a4) item specification count source two-phase pulse signals input to taiin or taiout pin count operation ? increment or decrement can be selected by two-phase pulse signal ? when the timer overflows or underflows, it reloads the reload register contents and con- tinues counting. when operating in free-running mode, the timer continues counting with- out reloading. divide ratio ? 1/ (ffffh - n + 1) for increment ? 1/ (n + 1) for decrement n: set value of the tai register 0000h to ffffh count start condition set the tais bit in the tabsr register to 1 (start counting) count stop condition set the tais bit to 0 (stop counting) interrupt request generation timing timer overflow or underflow taiin pin function two-phase pulse input taiout pin function two-phase pulse input read from timer count value can be read by reading timer a2, a3, or a4 register write to timer when not counting value written to the tai register is written to both reload register and counter when counting value written to the tai register is written to only reload register (transferred to counter when reloaded next) select function (1) normal processing operation (timer a2 and timer a3) the timer increments rising edges or decrements falling edges on the tajin pin when input signals on the tajout pin is ?h?. multiply-by-4 processing operation (timer a3 and timer a4) if the phase relationship is such that takin pin goes ?h? when the input signal on the tak- out pin is ?h,? the timer increments rising and falling edges on pins takout and takin. if the phase relationship is such that the takin pin goes ?l? when the input signal on the takout pin is ?h,? the timer counts down rising and falling edges on pins takout and takin. counter initialization by z-phase input (timer a3) the timer count value is initialized to 0 by z-phase input. tajout increment increment increment decrement decrement decrement tajin takout takin increment all edges decrement all edges increment all edges decrement all edges rej09b0392-0064 rev.0.64 oct 12, 2007 page 147 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.12 registers ta2mr to ta4mr in event counter mode (when using two-phase pulse signal processing with timers a2, a3, and a4) b7 1 0 0 0 1 0 b6 b5 b4 b1 b2 b3 symbol ta2mr to ta4mr address 0338h to 033ah after reset 00h b0 function bit symbol bit name rw tck1 rw rw count operation type select bit tck0 timer ai mode regist er (i = 2 to 4) (when using two-phase pu lse signal processing) 0 : reload type 1 : free-run type notes : 1. the tck1 bit can be set only for timer a3 mode regi ster. no matter how this bit is set, timers a2 and a4 always operate in normal processing mode a nd x4 processing mode, respectively. 2. to use two-phase pulse signal processing, following the register setting below: ? set the taip bit in the udf register to 1 (two -phase pulse signal processing function enabled). ? set bits taitgh and taitgl in the trgsr register to 00b (taiin pin input). ? set the port direction bits for taiin and taiout to 0 (input mode). rw mr1 rw mr0 set to 0 to use two-phas e pulse signal processing set to 0 to use two-phas e pulse signal processing two-phase pulse signal processing operation type select bit (1, 2) 0 : normal processing operation 1 : multiply-by-4 pr ocessing operation rw mr2 set to 1 to use two-phas e pulse signal processing rw mr3 set to 0 to use two-phas e pulse signal processing tmod1 tmod0 b1 b0 0 1 : event counter mode operation mode select bit rw rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 148 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers 15.1.2.1 counter initialization by two-phase pulse signal processing this function initializes the timer count value to 0 by z-phase (counter initialization) input during two- phase pulse signal processing. this function can only be used in timer a3 even t counter mode during two-phase pulse signal pro- cessing, free-running type, multiply-by-4 proces sing, with z phase entered from the zp pin. counter initialization by z-phase input is enabled by writing 0000h to the ta3 register and setting the tazie bit in the onsf register to 1 (z-phase input enabled). counter initialization is accomplished by detecting z-phase input edge. the active edge can be cho- sen to be the rising or falling edge by using the pol bit in the int2ic register. the z-phase pulse width applied to the zp pin must be equal to or greater t han one clock cycle of timer a3 count source. the counter is initialized at the next count timing after recognizing z-phase input. figure 15.13 shows the relationship between the two-phase puls e (a phase and b phase) and the z phase. if timer a3 overflow or underflow coincides with the counter initialization by z phase input, a timer a3 interrupt request is generated twice in succession. do not use timer a3 interrupt when using this function. figure 15.13 relationship between the two-phase pulse (a phase and b phase) and the z phase ta3out (a phase) ta3in (b phase) count source input equal to or greater than one clock cycle of count source zp (1) note : 1. this timing diagram is for the case where the pol bit in the int2ic register = 1 (rising edge). timer a3 mm + 1 1 2 3 4 5 rej09b0392-0064 rev.0.64 oct 12, 2007 page 149 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers 15.1.3 one-shot timer mode in one-shot timer mode, the timer is activated only once by one trigger (see ta ble 15.4). when the trig- ger occurs, the timer starts up and continues oper ating for a given period. figure 15.14 shows the taimr register in one-shot timer mode. i = 0 to 4 table 15.4 specifications in one-shot timer mode item specification count source f1timab, f2timab, f8tim ab, f32timab, f64timab, foco-s, fc32 count operation ? decrement ? when the counter reaches 0000h, it stops counting after reloading a new value. ? if a trigger occurs when counting, the timer reloads a new count and restarts counting. divide ratio 1/n n: set value of the tai register 0000h to ffffh however, the counter does not work if the divide-by-n value is set to 0000h. count start condition the tais bit in the tabsr regi ster = 1 (start counting) and one of the following triggers occurs. ? external trigger input from the taiin pin ? timer b2 overflow or underflow, timer aj (j = i - 1, except j = 4 if i = 0) overflow or underflow, timer ak (k = i + 1, except k = 0 if i = 4) overflow or underflow ? the taios bit in the onsf register is set to 1 (timer starts) count stop condition ? when the counter is reloaded after reaching 0000h ? the tais bit is set to 0 (stop counting) interrupt request generation timing when the counter reaches 0000h taiin pin function i/o port or trigger input taiout pin function i/o port or pulse output read from timer an indeterminate value is read by reading the tai register write to timer ? when not counting and until the 1st count source is input after counting starts value written to the tai register is wri tten to both reload register and counter ? when counting (after 1st count source input) value written to the tai register is written to only reload register (transferred to counter when reloaded next) select function ? pulse output function the timer outputs low when not counting and high when counting. ? output polarity control while the output polarity of taiout pin is inverted (the tais bit is set to 0 (stop counting)), the pin outputs high. rej09b0392-0064 rev.0.64 oct 12, 2007 page 150 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.14 taimr register in one-shot timer mode b7 0 1 0 b6 b5 b4 b1 b2 b3 symbol ta0mr to ta4mr address 0336h to 033ah after reset 00h b0 function bit symbol bit name rw timer ai mode regist er (i = 0 to 4) notes : 1. the ta0out pin is n-channel open drain output. 2. valid when bits taitgh and taitgl in the onsf register or trgsr register are set to 00b (taiin pin input). 3. set the port direction bit for the taiin pin to 0 (input mode). 4. selected by the pclk0 bit in the pclkr register. 5. valid when the tcs3 bit or tcs7 bit in re gisters tacs0 to tacs2 is set to 0 (tck0, tck1 enabled). rw b1 b0 1 0 : one-shot timer mode operation mode select bit rw tmod1 tmod0 pulse output function select bit rw mr0 0 : no pulse output (taiout pin functions as i/o port) 1 : pulse output (1) (taiout pin functions as a pulse output pin) rw mr1 external trigger select bit (2) 0 : falling edge of input signal to taiin pin (3) 1 : rising edge of input signal to taiin pin (3) tck0 mr3 rw set to 0 in one-shot timer mode tck1 rw mr2 trigger select bit 0 : taios bit enabled 1 : selected by bits taitgh and taitgl rw count source select bit (5) b7 b6 0 0 : f1timab or f2timab (4) 0 1 : f8timab 1 0 : f32timab 1 1 : fc32 rej09b0392-0064 rev.0.64 oct 12, 2007 page 151 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers 15.1.4 pulse width m odulation (pwm) mode in pwm mode, the timer outputs pulses of a given width in succession (see table 15.5). the counter functions as either 16-bit pulse width modulator or 8-bit pulse wi dth modulator. figure 15.15 shows taimr register in pwm mode. figures 15.16 and 15.17 show an example of 16-bit pulse width mod- ulator operation and 8-bit pulse width modulator operation, respectively. i = 0 to 4 table 15.5 specifications in pwm mode item specification count source f1timab, f2timab, f8tim ab, f32timab, f64timab, foco-s, fc32 count operation ? decrement (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new value at a rising edge of pwm pulse and continues counting. ? the timer is not affected by a trigger that occurs during counting. 16-bit pwm ? pulse width n / fj n: set value of the tai register ? cycle time (2 16 - 1) / fj fixed fj: count source frequency ( 1timab, f2timab, f8timab, f32timab, f64timab, foco-s, fc32 ) 8-bit pwm ? pulse width n (m+1) / fj n: set value of the tai register high-order address ? cycle time (2 8 -1) (m+1) / fj m: se t value of the tai register low-order address count start condition ? the tais bit of the t absr register is set to 1 (start counting) ? the tais bit = 1 and external trigger input from the taiin pin ? the tais bit = 1 and one of the following external triggers occurs timer b2 overflow or underflow, timer aj (j = i - 1, except j = 4 if i = 0) overflow or underflow, timer ak (k = i + 1, except k = 0 if i = 4) overflow or underflow count stop condition the tais bit is set to 0 (stop counting) interrupt request generation timing on the falling edge of pwm pulse taiin pin function i/o port or trigger input taiout pin function pulse output read from timer an indeterminate value is read by reading the tai register write to timer ? when not counting value written to the tai register is wri tten to both reload register and counter ? when counting value written to the tai register is written to only reload register (transferred to counter when reloaded next) select function ? output polarity control while the output polarity of taiout pin is inverted (the tais bit is set to 0 (stop counting)), the pin outputs high. rej09b0392-0064 rev.0.64 oct 12, 2007 page 152 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.15 taimr register in pwm mode b7 1 1 b6 b5 b4 b1 b2 b3 symbol ta0mr to ta4mr address 0336h to 033ah after reset 00h b0 function bit symbol bit name rw timer ai mode regist er (i = 0 to 4) notes : 1. the ta0out pin is n-channel open drain output. 2. valid when bits taitgh and taitgl bit in the onsf register or trgsr register are set to 00b (taiin pin input). 3. set the port direction bit for the taiin pin to 0 (input mode). 4. set this bit to 1 (pulse output) to output pwm pulse. 5. selected by the pclk0 bit in the pclkr register. 6. valid when the tcs3 bit or tcs7 bit in registers tacs0 to tacs2 is set to 0 (tck0, tck1 enabled). rw b1 b0 1 1 : pwm mode operation mode select bit rw tmod1 tmod0 rw mr3 16 / 8-bit pwm mode select bit 0 : functions as a 16-bit pulse width modulator 1 : functions as an 8-bit pulse width modulator rw mr1 external trigger select bit (2) 0 : falling edge of input signal to taiin pin (3) 1 : rising edge of input signal to taiin pin (3) tck0 tck1 rw mr2 trigger select bit 0 : write 1 to the tais bit in the tabsr register 1 : selected by bits taitgh and taitgl rw count source select bit (6) b7 b6 0 0 : f1timab or f2timab (5) 0 1 : f8timab 1 0 : f32timab 1 1 : fc32 pulse output function select bit (4) rw mr0 0 : no pulse output (taiout pin functions as i/o port) 1 : pulse output (1) (taiout pin functions as a pulse output pin) rej09b0392-0064 rev.0.64 oct 12, 2007 page 153 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.16 example of 16-bit pulse width modulator operation figure 15.17 example of 8-bit pulse width modulator operation 1 / f j (2 16 - 1) count source input signal to taiin pin trigger is not generated by this signal. ?h? ?l? 1 / f j n ir bit in taiic register ?1? ?0? set to 0 upon accepting an interrupt request or by writing in program. fj: count source frequency (f1timab, f2timab, f8timab, f32timab, f64timab, foco-s, fc32) notes : 1. n = 0000h to fffeh 2. this timing diagram is for the case where the tai register is 0003h, bits taitgh and taitgl in the onsf register or trgsr register are 00b (input to the taiin pin), the mr1 bit in the taimr register is 1 (rising edge), and the mr2 bit in the taimr register is 1 (trigger selected by bits taitgh and taitgl). i = 0 to 4 tofsi: bit in the tapofs register pwm pulse output from taiout pin ?h? ?l? when tofsi = 1 (waveform output = ?l? active, inverted) ?h? ?l? when tofsi = 0 (waveform output = ?h? active, not inverted) count source (1) input signal to taiin pin 8-bit prescaler underflow signal (2) ?h? ?h? ?l? ?l? 1 / f j (m + 1) (2 8 - 1) 1 / f j (m+1) set to 0 upon accepting an interrupt request or by writing in program. 1 / f j (m + 1) n ir bit in taiic register ?1? ?0? notes : 1. the 8-bit prescaler counts the count source. 2. the 8-bit pulse width modulator counts underflow signals of the 8-bit prescaler. 3. m = 00h to ffh, n=00h to feh 4. this timing diagram is for the case where the tai register is 0202h, bits taitgh and taitgl in the onsf register or trgsr register are 00b (input to t he taiin pin), the mr1 bit in the taimr register is 0 (falling edge), and the mr2 bit in the taimr register is 1 (trigger selected by bits taitgh and taitgl). i = 0 to 4 tofsi: bit in tapofs register fj: count source frequency (f1timab, f2timab, f8timab, f32timab, f64timab, foco-s, fc32) ?h? ?l? when tofsi = 1 (waveform output = ?l? active, inverted) ?h? ?l? pwm pulse output from taiout pin when tofsi = 0 (waveform output = ?h? h ctive, not inverted) rej09b0392-0064 rev.0.64 oct 12, 2007 page 154 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers 15.2 timer b figure 15.18 shows timer b block diagram. figures 15 .19 to 15.21 show registers related to timer b. timer b supports the following three modes. use bits tmod1 and tmod0 in the tbimr register (i = 0 to 5) to select the desired mode. ? timer mode : the timer counts an internal count source. ? event counter mode : the timer counts pulses from an external device or overflows or underflows of other timers. ? pulse period, pulse width measurement mode: the timer measures pulse period or pulse width of an external signal. figure 15.18 timer b block diagram select clock source i = 0 to 5 j = i - 1; however, j = 2 when i = 0, j = 5 when i = 3 tbiin tbis counter reset circuit polarity switching and edge pulse tck1 to tck0, tmod1 to tmod0 : bits in the tbimr register tbis : bits in the tabsr register or tbsr register tcs0 to tcs7 : bits in registers tbcs0 to tbcs3 tck1 to tck0 00 01 f1timab or f2timab f8timab f32timab fc32 10 11 000 001 f1timab or f2timab f8timab f32timab fc32 010 110 or tcs6 to tcs4 tcs2 to tcs0 f64timab foco-s 011 101 01: event counter 00: timer 10: pulse period and pulse width measurement tck1 tbj overflow (1) 1 0 tmod1 to tmod0 0 1 tcs3 or tcs7 note : 1. overflows or underflows. data bus counter reload register tbi tbj timer b0 timer b2 timer b1 timer b0 timer b2 timer b1 timer b3 timer b5 timer b4 timer b3 timer b5 timer b4 rej09b0392-0064 rev.0.64 oct 12, 2007 page 155 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.19 register tb0mr to tb5mr and tb0 to tb5 b7 b6 b5 b4 b1 b2 b3 symbol tb0mr to tb2mr tb3mr to tb5mr address 033bh to 033dh 031bh to 031dh after reset 00xx0000b 00xx0000b b0 function bit symbol bit name rw timer bi mode regist er (i = 0 to 5) note : 1. valid when the tcs3 bit or tcs7 bit in registers tacs0 to tacs2 is set to 0 (tck0, tck1 enabled). no register bit. if necessary, set to 0. read as undefined value mr1 ? (b4) function varies with each operation mode b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period measurement mode pulse width measurement mode 1 1 : do not set operation mode select bit rw rw tmod1 tmod0 function varies with each operation mode mr0 rw ? rw tck1 tck0 mr3 ro rw rw count source select bit (1) (function varies with each operation mode) (b15) b7 b7 symbol tb0 tb1 tb2 tb3 tb4 tb5 address 0331h to 0330h 0333h to 0332h 0335h to 0334h 0311h to 0310h 0313h to 0312h 0315h to 0314h after reset indeterminate indeterminate indeterminate indeterminate indeterminate indeterminate b0 setting range mode function rw timer bi register (i = 0 to 5) (1) 0000h to ffffh divide the count source by n + 1 where n = set value timer mode rw notes : 1. access to the register in 16-bit units. 2. the timer counts pulses from an external devi ce or overflows or underflows of other timers. 3. set it when the tbis bit in the tabsr or tbsr register is se t to 0 (count stops). 4. read only (ro) when the tbis bit in the tabsr or tbsr register is set to 1 (count starts). (b8) b0 0000h to ffffh divide the count source by n + 1 where n = set value (2) event counter mode rw 0000h to ffffh (3) measures a pulse period or width pulse period measurement mode pulse width measurement mode rw (4) rej09b0392-0064 rev.0.64 oct 12, 2007 page 156 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.20 register tabsr, tbsr, and cpsrf b7 b6 b5 b4 b1 b2 b3 symbol tabsr address 0320h after reset 00h b0 function bit symbol bit name rw count start flag 0 : stop counting 1 : start counting tb0s tb2s timer a3 count start flag timer b2 count start flag rw rw rw rw ta4s rw ta3s timer b0 count start flag timer b1 count start flag tb1s timer a4 count start flag timer a1 count start flag ta1s rw timer a2 count start flag rw ta2s timer a0 count start flag ta0s rw pofs0 no register bits. if necessary, set to 0. read as undefined value ? (b4-b0) ? b7 b6 b5 b4 b1 b2 b3 symbol tbsr address 0300h after reset 000xxxxxb b0 function bit symbol bit name rw timer b3, b4, b5 count start flag timer b5 count start flag rw tb5s timer b3 count start flag tb3s rw timer b4 count start flag rw tb4s 0 : stop counting 1 : start counting clock prescaler reset flag b7 b6 b5 b4 b1 b2 b3 symbol cpsrf address 0015h bit symbol bit name rw after reset 0xxxxxxxb b0 function ? (b6-b0) ? no register bits. if necessary, set to 0. read as undefined value cpsr rw clock prescaler reset flag initializing the clock prescaler. (read as 0) rej09b0392-0064 rev.0.64 oct 12, 2007 page 157 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.21 registers tbcs0, tbcs1, tbcs2, and tbcs3 b7 b6 b5 b4 b1 b2 b3 symbol tbcs0 tbcs2 address 01c8h 01e8h after reset 00h 00h b0 function bit symbol bit name rw timer b count source select register 0, timer b count source select register 2 tbcs0 register: i = 0, j = 1 tbcs2 register: i = 3, j = 4 note : 1. set this value at the pclk0 bit in the pclkr register. b2 b1 b0 0 0 0 : f1timab or f2timab (1) 0 0 1 : f8timab 0 1 0 : f32timab 0 1 1 : f64timab 1 0 0 : do not set 1 0 1 : foco-s 1 1 0 : f c32 1 1 1 : do not set tbi count source select bit tcs1 tcs2 tcs0 rw rw rw rw tcs3 1 : tck0, tck1 enabled, tcs0 to tcs2 disabled 0 : tck0, tck1 disabled, tcs0 to tcs2 enabled tbi count source option specified bit b6 b5 b4 0 0 0 : f1timab or f2timab (1) 0 0 1 : f8timab 0 1 0 : f32timab 0 1 1 : f64timab 1 0 0 : do not set 1 0 1 : foco-s 1 1 0 : f c32 1 1 1 : do not set tbj count source select bit tcs5 tcs6 tcs4 rw rw rw rw tcs7 1 : tck0, tck1 enabled, tcs4 to tcs6 disabled 0 : tck0, tck1 disabled, tcs4 to tcs6 enabled tbj count source option specified bit b7 b6 b5 b4 b1 b2 b3 symbol tbcs1 tbcs3 address 01c9h 01e9h after reset x0h x0h b0 function bit symbol bit name rw timer b count source select register 1, timer b count source select register 3 tbcs1 register: i = 2 tbcs3 register: i = 5 note : 1. set this value at the pclk0 bit in the pclkr register. b2 b1 b0 0 0 0 : f1timab or f2timab (1) 0 0 1 : f8timab 0 1 0 : f32timab 0 1 1 : f64timab 1 0 0 : do not set 1 0 1 : foco-s 1 1 0 : fc32 1 1 1 : do not set tbi count source select bit tcs1 tcs2 tcs0 rw rw rw rw tcs3 1 : tck0, tck1 enabled, tcs0 to tcs2 disabled 0 : tck0, tck1 disabled, tcs0 to tcs2 enabled tbi count source option specified bit ? ? (b7-b4) no register bits. if necessary, set to 0. read as undefined value rej09b0392-0064 rev.0.64 oct 12, 2007 page 158 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers 15.2.1 timer mode in timer mode, the timer counts a c ount source generated internally (see table 15.6 ). figure 15.22 shows the tbimr register in timer mode. i = 0 to 5 note: 1. bits tb0s to tb2s are assigned to bits 5 to 7 in the tabsr register, and bits tb3s to tb5s are assigned to bits 5 to 7 in the tbsr register. table 15.6 specifications in timer mode item specification count source f1timab, f2timab, f8ti mab, f32timab, f64timab, foco-s, fc32 count operation ? decrement ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1 / (n + 1) n: set value of the tbi register 0000h to ffffh count start condition set the tbis bit (1) to 1 (start counting) count stop condition set the tbis bit to 0 (stop counting) interrupt request generation timing timer underflow tbiin pin function i/o port read from timer count value can be read by reading the tbi register write to timer ? when not counting value written to the tbi register is written to both reload register and counter ? when counting value written to the tbi register is written to only reload register (transferred to counter when reloaded next) rej09b0392-0064 rev.0.64 oct 12, 2007 page 159 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.22 tbimr register in timer mode b7 0 0 0 0 b6 b5 b4 b1 b2 b3 symbol tb0mr to tb2mr tb3mr to tb5mr address after reset b0 function bit symbol bit name rw timer bi mode regist er (i = 0 to 5) notes : 1. selected by the pclk0 bit in the pclkr register. 2. valid when the tcs3 bit or tcs7 bit in registers tacs0 to tacs2 is se t to 0 (tck0, tck1 enabled). ? ? rw b1 b0 0 0 : timer mode operation mode select bit rw tmod1 tmod0 033bh to 033dh 031bh to 031dh 00xx0000b 00xx0000b ro mr3 rw tck0 rw set to 0 in timer mode rw mr1 mr0 no register bit. if necessary, set to 0. read as undefined value write 0 in timer mode. read as undefined value in timer mode count source select bit (2) b7 b6 0 0 : f1timab or f2timab (1) 0 1 : f8timab 1 0 : f32timab 1 1 : fc32 rw tck1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 160 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers 15.2.2 event counter mode in event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see table 15.7 ). figure 15.23 shows the tbimr register in event counter mode. i = 0 to 5 note: 1. bits tb0s to tb2s are assigned to bits 5 to 7 in the tabsr register, and bits tb3s to tb5s are assigned to bits 5 to 7 in the tbsr register. table 15.7 specifications in event counter mode item specification count source ? external signals in put to tbiin pin (effective edge rising edge , falling edge, or both rising and falling edges) can be selected in a program) ? timer bj overflow or underflow (j = i - 1, except j = 2 if i = 0, j = 5 if i = 3) count operation ? decrement ? when the timer underflows, it reloads the reload register contents and con- tinues counting. divide ratio 1 / (n + 1) n: set va lue of the tbi register 0000h to ffffh count start condition set the tbis bit (1) to 1 (start counting) count stop condition set the tbis bit to 0 (stop counting) interrupt request generation timing timer underflow tbiin pin function count source input read from timer count value can be read by reading the tbi register. write to timer ? when not counting value written to the tbi register is writ ten to both reload register and counter ? when counting value written to the tbi register is written to only reload register (transferred to counter when reloaded next) rej09b0392-0064 rev.0.64 oct 12, 2007 page 161 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.23 tbimr register in event counter mode b7 1 0 b6 b5 b4 b1 b2 b3 symbol tb0mr to tb2mr tb3mr to tb5mr address after reset b0 function bit symbol bit name rw timer bi mode regist er (i = 0 to 5) notes : 1. valid when the tck1 bit = 0 (input from tbiin pi n). if the tck1 bit = 1 (tbj overflow or underflow), these bits can be set to 0 or 1. 2. set the port direction bit for the tbiin pin to 0 (input mode). ? ? no register bit. if necessary, set to 0. read as undefined value rw b1 b0 0 1 : event counter mode operation mode select bit rw tmod1 tmod0 count polarity select bit (1) b3 b2 0 0 : counts falling edges of external signal 0 1 : counts rising edges of external signal 1 0 : counts falling and rising edges external signal 1 1 : do not set to this value 033bh to 033dh 031bh to 031dh 00xx0000b 00xx0000b mr1 mr0 rw rw ro mr3 write 0 in event counter mode. read as undefined value in event counter mode rw tck0 invalid in event counter mode. set 0 or 1 rw tck1 event clock select 0 : input from tbiin pin (2) 1 : tbj overflow or underflow (j = i ? 1; however, j = 2 if i = 0, j = 5 if i = 3) rej09b0392-0064 rev.0.64 oct 12, 2007 page 162 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers 15.2.3 pulse period and pulse width measurement modes in pulse period and pulse width measurement mode, th e timer measures pulse period or pulse width of an external signal (see table 15.8 ). figure 15.24 shows the tbimr register in pulse period and pulse width measurement mode. figure 15.25 shows the ope ration timing when measuring a pulse period. figure 15.26 shows the operation timing when measuring a pulse width. i = 0 to 5 notes: 1. interrupt request is not generated when the first effective edge is input after the timer started count- ing. 2. value read from the tbi register is indeterminate until the second valid edge is input after the timer starts counting. 3. bits tb0s to tb2s are assigned to bits 5 to 7 in the tabsr register, and bits tb3s to tb5s are assigned to bits 5 to 7 in the tbsr register. table 15.8 specifications in pulse period and pulse width measurement mode item specification count source f1timab, f2timab, f8timab, f32timab, f64timab, foco-s, fc32 count operation ?increment ? counter value is transferred to reload register at an effective edge of measurement pulse. the counter value is set to 0000h to continue counting. count start condition set the tbis bit (3) to 1 (start counting) count stop condition set the tbis bit to 0 (stop counting) interrupt request generation timing ? when an effective edge of measurement pulse is input (1) timer overflow. when an overflow occurs, the mr3 bit in the tbimr register is set to 1 (overflowed) simultaneously. tbiin pin function measurement pulse input read from timer contents of the reload register (measurem ent result) can be read by reading the tbi register (2) write to timer value written to the tbi regi ster is written to neither reload register nor counter rej09b0392-0064 rev.0.64 oct 12, 2007 page 163 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.24 tbimr register in pulse period and pulse width measurement mode b7 0 1 b6 b5 b4 b1 b2 b3 symbol tb0mr to tb2mr tb3mr to tb5mr address 033bh to 033dh 031bh to 031dh after reset 00xx0000b 00xx0000b b0 function bit symbol bit name rw timer bi mode regist er (i = 0 to 5) notes : 1. this flag is indeterminate after reset. when the tb is bit in the tabsr register or tbsr register is set to 1 (start counting), the mr3 bit is cleared to 0 (no overflow) by writing to the tbimr register. the mr3 bit cannot be set to 1 in a program. 2. selected by the pclk0 bit in the pclkr register. 3. valid when the tcs3 bit or tcs7 bit in registers tacs0 to tacs3 is set to 0 (tck0, tck1 enabled). rw b1 b0 1 0 : pulse period, pulse width measurement mode operation mode select bit rw tmod1 tmod0 count source select bit (3) b7 b6 0 0 : f1timab or f2timab (2) 0 1 : f8timab 1 0 : f32timab 1 1 : fc32 ? ? no register bit. if necessary, set to 0. read as undefined value mr3 ro timer bi overflow flag (1) 0 : no overflow 1 : overflow tck0 rw tck1 rw measurement mode select bit b3 b2 0 0 : pulse period measurement (measurement between a falling edge and the next falling edge of measured pulse) 0 1 : pulse period measurement (measurement between a rising edge and the next rising edge of measured pulse) 1 0 : pulse width measurement (measurement between a falling edge and the next rising edge of measured pulse and between a rising edge and the next falling edge) 1 1 : do not set to this value rw mr1 rw mr0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 164 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 15. timers figure 15.25 operation timing when measuring a pulse period figure 15.26 operation timing when measuring a pulse width count source measurement pulse tbis bit ir bit in tbiic register timing at which counter reaches 0000h ?1? ?h? ?1? transfer (indeterminate value) ?l? ?0? ?0? mr3 bit in tbimr register ?1? ?0? notes : 1. counter is initialized at completion of measurement. 2. timer has overflowed. 3. this timing diagram is for the case where bits mr1 and mr0 in the tbimr register are 00b (measure the interval from falling edge to falling edge of the measurement pulse). (note 1) (note 1) set to 0 upon accepting an interrupt request or by writing in program (note 2) transfer (measured value) bits tb0s to tb2s are assigned to bits 5 to 7 in the tabsr register, and bits tb3s to tb5s are assigned to bits 5 to 7 in the tabsr register. i = 0 to 5 reload register counter transfer timing measurement pulse ?h? count source timing at which counter reaches 0000h ?1? ?1? transfer (indeterminate value) transfer (measured value) ?l? ?0? ?0? ?1? ?0? notes : 1. counter is initialized at completion of measurement. 2. timer has overflowed. 3. this timing diagram is for the case where bits mr1 and mr0 in the tbimr register are 10b (measure the interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the measurement pulse). (note 1) (note 1) (note 1) (note 1) transfer (measured value) (note 2) tbis bit ir bit in tbiic register mr3 bit in tbimr register set to 0 upon accepting an interrupt request or by writing in program bits tb0s to tb2s are assigned to bits 5 to 7 in the tabs r register, and bits tb3s to tb5s are assigned to bits 5 to 7 in the tabsr register. i = 0 to 5 reload register counter transfer timing transfer (measured value) rej09b0392-0064 rev.0.64 oct 12, 2007 page 165 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 16. three-phase motor control timer function 16. three-phase motor control timer function timers a1, a2, a4, and b2 can be used to output thr ee-phase motor drive waveforms. table 16.1 lists the three-phase motor control timer functions specificat ions. figure 16.1 shows the three-phase motor con- trol timer functions block diagram. also, the related registers are shown on figures 16.2 to 16.7. notes: 1. forced cutoff with sd input is effective when th e ivpcr1 bit in the tb2sc register is set to 1 (three- phase output forcible cutoff by sd input enabled). if an ?l? signal is applied to the sd pin when the ivpcr1 bit is 1, the related pins go to a high-imp edance state regardless of which functions of those pins are being used. 2. related pins: p7_2/clk2/ta1out/v, p7_3/ cts2 / rts2 /ta1in/ v , p7_4/ta2out/w, p7_5/ta2in/ w , p8_0/ta4out/rxd5/scl5/u, p8_1/ta4in/ cts5 / rts5 / u table 16.1 three-phase motor control timer functions specifications item specification three-phase waveform output pin six pins (u, u , v, v , w, w ) forced cutoff input (1) input ?l? to the sd pin used timers timer a4, a1, a2 (used in one-shot timer mode) timer a4: u- and u -phase waveform control timer a1: v- and v -phase waveform control timer a2: w- and w -phase waveform control timer b2 (used in timer mode) carrier wave cycle control dead time timer (3 eight-bit ti mers and shared reload register) dead time control output waveform triangular wave modulation, sawtooth wave modulation ? enable to output ?h? or ?l? for one cycle ? enable to set positive-phase level and negative-phase level independently carrier wave cycle triangular wave modulation : count source x (m + 1) x 2 sawtooth wave modulation : count source x (m + 1) m: setting value of the tb2 register, 0000h to ffffh count source: f1timab, f2timab, f8timab, f32timab, f64timab, foco-s, fc32 three-phase pwm output width triangular wave modulation: count source x n x 2 sawtooth wave modulation: count source x n n: setting value of registers ta4, ta1, and ta2 (of registers ta4, ta41, ta1, ta11, ta2, and ta21 when setting the inv11 bit to 1), 0001h to ffffh count source: f1timab, f2timab, f8timab, f32timab, f64timab, foco-s, fc32 dead time count source x p, or no dead time p: setting value of the dtt register, 01h to ffh count source: f1timab, f2timab, f1timab divided by 2, f2timab divided by 2 active level enable to select ?h? or ?l? positive and negative- phase concurrent active disable function positive-and negative-phases conc urrent active disable function positive-and negative-phases conc urrent active detect function interrupt frequency timer b2 interrupt is generated every q times q: carrier wave cycle-to-cycle basis, 1 to 15 rej09b0392-0064 rev.0.64 oct 12, 2007 page 166 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 16. three-phase motor control timer function figure 16.1 three-phase motor control timer functions block diagram timer b2 timer b2 underflow circuit to set interrupt generation frequency inv07 1/2 f1 or f2 u-phase output control circuit dub1 bit dub0 bit d q t d q t d q t d q t du1 bit du0 bit v-phase output control circuit (one-shot timer mode) timer a4 control signal timer a4 counter selector ta41 register ta4 register inv11 t q (one-shot timer mode) timer a4 control signal selector ta11 register ta1 register inv11 t q timer a1 counter inv06 inv06 (one-shot timer mode) timer a2 one- shot pulse timer a2 counter selector ta21 register ta2 register inv11 t q inv06 dead time timer n = 1 to 255 reload register n = 1 to 255 dead time timer n = 1 to 255 dead time timer n = 1 to 255 d q t d q t w-phase output control circuit d q t d q t d q t d q t inv01 inv11 inv00 reload control signal for timer a1 timer b2 interrupt request bit ictb2 register n = 1 to 15 inv13 write signal to timer b2 inv10 (timer mode) inv04 reset nmi inv05 d q t r value to be written to inv03 bit write signal to inv03 bit inv02 inv03 inverse control inverse control inverse control inverse control inverse control inverse control inv14 u u v v w w 1 0 ictb2 counter n = 1 to 15 pwcon inv12 start trigger signal for timers a1, a2, and a4 when setting the ta4s bit to 0, signal is set to 0. when setting the ta1s bit to 0, signal is set to 0. when setting the ta2s bit to 0, signal is set to 0. note: 1. transfer trigger is generated only when registers idb0 an d idb1 are set and the first timer b2 underflows, if the inv06 bit is set to 0 (triangular wave modulation). w-phase output signal w-phase output signal v-phase output signall v-phase output signal u-phase output signal u-phase output signal trigger trigger trigger trigger trigger trigger trigger three-phase output shift register (u phase) transfer trigger (1) trigger trigger inv00 to inv07 : bits in the invc0 register inv10 to inv15 : bits in the invc1 register dui, dubi : bits in the idbi register (i = 0,1) ta1s to ta4s : bits in the tabsr register pwcom : bits in the tb2sc register timer a2 one-shot pulse timer a1 one-shot pulse timer a4 one-shot pulse 1 0 reload reload reload reload reload reload switching to p8_0, p8_1 and p7_2 to p7_5 is not shown in this diagram. rej09b0392-0064 rev.0.64 oct 12, 2007 page 167 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 16. three-phase motor control timer function figure 16.2 invc0 register b7 b6 b5 b4 b1 b2 b3 three-phase pwm control register 0 (1) symbol invc0 address 0308h bit symbol bit name rw inv00 after reset 00h rw b0 function interrupt enable output polarity select bit inv01 rw rw 0 : ictb2 counter is decremented by one when timer b2 underflows 1 : selected by the inv00 bit (3) interrupt enable output specification bit (2) 0 : the ictb2 counter is decremented by one on the rising edge of timer a1 reload control signal 1 : the ictb2 counter is decremented by one on the falling edge of timer a1 reload control signal (3) inv02 mode select bit (4) 0 : no three-phase control timer functions 1 : three-phase control timer function (5) inv03 output control bit (6) 0 : disables three-phase control timer output (5) 1 : enables three-phase control timer output modulation mode select bit (8) 0 : triangular wave modulation mode 1 : sawtooth wave modulation mode (9) inv06 rw rw rw inv04 positive-and negative- phases concurrent active disable function bit 0 : enables concurrent active output 1 : disables concurrent active output inv05 positive-and negative- phases concurrent active output detect flag 0 : not detected 1 : detected (7) rw notes : 1. set the invc0 register after the prc1 bit in the prcr register is set to 1 (write enabled). rewrite bits inv00 to inv02 and inv06 when timers a1, a2, a4 and b2 stop. 2. set the inv01 bit to 1 after setting the ictb2 register 3. bits inv00 and inv01 are enabled only when the inv 11 bit is set to 1 (three-phase mode 1). the ictb2 counter is decremented by one every time timer b2 underflows, regardless of in v00 and inv01 bit settings, when the inv11 bit is set to 0 (three-phase mode). when setting the inv01 bit to 1, set timer a1 count start flag to 1 before the first timer b2 underflow. when the inv00 bit is set to 1, the first interrupt is generated when timer b2 underflows n-1 times, if n is the valu e set in the ictb2 counter. subsequent interrupts are generated every n times timer b2 underflows. 4. set the inv02 bit to 1 to operate the dead ti me timer, u-, v-and w-phase out put control circuits and ictb2 counter. 5. when the invc03 bit is set to 1, the pins a pplied to u/v/w output three-phase pwm. pins u, u, v, v, w and w, including pins shared with othe r output functions, are all placed in high-impedance states when the following conditions are all met. ? the inv02 bit is set to 1 (three- phase motor control timer function) ? the inv03 bit is set to 0 (three-phase motor control timer output disabled) ? direction registers of each port are set to 0 (input mode) 6. the inv03 bit is set to 0 when the followings conditions are all met. ? reset ? a concurrent active state occurs while the inv04 bit is set to 1 ? the inv03 bit is set to 0 by program ? a signal applied to the sd pin changes ?h? to ?l? when both bits invc04 and in vc05 are set to 1, the invc03 bit is set to 0. 7. the inv05 bit can not be set to 1 by program. set the inv04 bit to 0 as well when setting the inv05 bit to 0. 8. the following table describes how the inv06 bit works. software trigger select bit transfer trigger is generated when the inv07 bit is set to 1. trigger to the dead time timer is also generated when setting the inv06 bit to 1. read as 0. inv07 rw transfer trigger : timer b2 underflows and write to the inv07 bit, or write to the tb2 register when inv10 = 1 9. when the inv06 bit is set to 1, set the inv11 bit to 0 (three-phase mode 0) and the pwcon bit in the tb2sc register to 0 (reload timer b2 with timer b2 underflow). timing to transfer from registers idb0 and idb1 to three-phase output shift register timing to trigger the dead time timer when the inv16 bit = 0 mode item transferred once by generating a transfer trigger after setting registers idb0 and idb1 inv06 = 0 triangular wave modulation mode on the falling edge of a one-shot pulse of the timer a1, a2, or a4 transferred every time a transfer trigger is generated inv06 = 1 sawtooth wave modulation mode on the falling edge of a one-shot pulse of the timer a1, a2, or a4, and transfer a trigger inv13 bit enabled when the inv11 bit = 1 and the inv06 bit = 0 disabled rej09b0392-0064 rev.0.64 oct 12, 2007 page 168 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 16. three-phase motor control timer function figure 16.3 invc1 register b7 b6 b5 b4 b1 b2 b3 three-phase pwm control register 1 (1) symbol invc1 address 0309h bit symbol bit name rw after reset 00h b0 function inv10 rw rw 0 : timer b2 underflow 1 : timer b2 underflow and write to timer b2 timer a1, a2, and a4 start trigger select bit inv11 timer a1-1, a2-1 and a4-1 control bit (2) 0 : three-phase mode 0 (3) 1 : three-phase mode 1 inv12 dead time timer count source select bit 0 : f1timab or f2timab 1 : f1timab divided by 2 or f2timab divided by 2 dead time timer trigger select bit (5) 0 : falling edge of a one-shot pulse of timer a1, a2, and a4 1 : rising edge of the three-phase output shift register (u-, v-, w-phase) inv16 rw 0 ro inv13 carrier wave detect bit (4) 0 : timer a1 reload control signal is 0 1 : timer a1 reload control signal is 1 inv14 output polarity control bit 0 : active ?l? of an output waveform 1 : active ?h? of an output waveform rw notes : 1. rewrite the invc1 register after the prc1 bit in the prcr register is set to 1 (write enabled). rewrite while the timers a1, a2, a4, and b2 stop. 2. the following table lists how the inv11 bit works. 3. when the inv06 bit is set to 1 (sawtooth wave modulation mode), set the inv11 bit to 0 (three-phase mode 0). also, when the inv11 bit is set to 0, set the pwcon bit in the tb2sc register to 0 (timer b2 is reloaded when timer b2 underflows). 4. the inv13 bit is enabled only when the inv06 bit is set to 0 (triangular wave modulation mode) and the inv11 bit to 1 (three-phase mode 1). 5. if the following conditions are all met, set the inv16 bit to 1 (rising edge of the three-phase output shift registe r). ? the inv15 bit is set to 0 (dead time timer enabled) ? the dij bit and dibj bit always have different values when the inv03 bi t is set to 1 (the positive-phase and negative-phase always output opposite level si gnals) (i = u, v or w, j = 0, 1). if above conditions are not met, set the inv16 bit to 0 (de ad time timer is triggered on the falling edge of a one- shot pulse of timers). rw ? (b7) reserved bit set to 0 rw inv15 dead time disable bit 0 : dead time enabled 1 : dead time disabled rw mode item inv13 bit inv11 = 0 three-phase mode 0 disabled inv11 = 1 three-phase mode 1 enabled when inv11 = 1 and inv06 = 0 registers ta11, ta21, and ta41 not used used bits inv00 and inv01 in the invc0 register disabled. the ictb2 counter is decremented whenever timer b2 underflows enabled rej09b0392-0064 rev.0.64 oct 12, 2007 page 169 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 16. three-phase motor control timer function figure 16.4 registers idb0, idb1, dtt, and ictb2 three-phase output buffer register i (1) (i = 0, 1) symbol idb0 idb1 address 030ah 030bh bit symbol rw dui after reset xx111111b xx111111b note : 1. values of registers idb0 and idb1 are transferred to the three-phase output shift register by a transfer trigger. after the transfer trigger occurs, the values written in the idb0 register determine each phase output signal first. then the value written in the idb1 register on the falling edge of timers a1, a2, and a4 one-shot pulse determines each phase output signal. dubi dvi dvbi dwi rw rw rw rw dwbi rw ? (b7-b6) ? rw b7 b6 b5 b4 b1 b2 b3 b0 bit name u-phase output buffer i v-phase output buffer i v-phase output buffer i w-phase output buffer i function write output level 0 : active level 1 : inactive level when read, the value of the three-phase shift register is read. no register bits. if necessary, set to 0. read as undefined value u-phase output buffer i w-phase output buffer i symbol dtt address 030ch after reset indeterminate function rw dead time timer (1, 2) notes : 1. use the mov instruction to set the dtt register. 2. the dtt register is enabled when the inv15 bit in the invc1 register is set to 0 (dead time enabled). no dead time can be set when the inv15 bit is set to 1 (dead time disabled). the inv06 bit in the invc0 register determines start trigger of the dtt register. setting range b7 b0 wo if setting value is n, the timer stops when counting n times a count source selected by the inv12 after start trigger occurs. positive or negative phase, which changes from inactive level to active level, shifts when the dead time timer stops. 1 to 255 timer b2 interrupt generation frequency set counter (1, 2, 3) symbol ictb2 address 030dh rw after reset indeterminate notes : 1. use the mov instruction to set the ictb2 register. 2. if the inv01 bit in the invco register is set to 1, set the ictb2 register when the tb2s bit in the tabsr register is set to 0 (timer b2 counter stopped). if the inv01 bit is set to 0 and the tb2s bit to 1 (timer b2 counter start), do not set the ictb2 register when timer b2 underflows. 3. if the inv00 bit is set to 1, the first interrupt is generated when timer b2 underflows n-1 times, n being the value set in the ictb2 counter. subsequent interrupts are generated every n times timer b2 underflows. b7 b0 function setting range ? no register bits. if necessary, set to 0 wo 1 to 15 when the inv01 bit is set to 0 (the ictb2 counter increments whenever timer b2 underflows) and the setting value is n, timer b2 interrupt is generated every nth time timer b2 underflow occurs. when the inv01 bit is set to 1 (the inv00 bit selects count timing of the ictb2 counter) and setting value is n, timer b2 interrupt is generated every nth time timer b2 underflow meeting the condition selected in the inv00 bit occurs. rej09b0392-0064 rev.0.64 oct 12, 2007 page 170 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 16. three-phase motor control timer function figure 16.5 registers ta1, ta2, ta4, ta11, ta21, ta41, and tb2sc b7 0 1 0 0 1 0 b6 b5 b4 b1 b2 b3 symbol ta1mr ta2mr ta4mr address 0337h 0338h 033ah after reset 00h 00h 00h b0 function bit symbol bit name rw rw mr1 timer ai mode register (i = 1, 2, 4) tmod1 rw set to 10b (one-shot timer mode) with the three-phase motor control timer function operation mode select bit tmod0 rw set to 0 with the three-phase motor control timer function external trigger select bit notes : 1. selected by the pclk0 bit in the pclkr register. 2. valid when bits tcs3 and tcs7 in registers tacs0 to tacs2 are set to 0. selected by bits tcs2 to tcs0 or tcs6 to tcs4 in registers tacs0 to tacs2 when bits tcs3 and tcs7 are set to 1. (refer to figure 15.8 registers tacs0 and tacs and figure 15.9 tacs2 register ). rw mr0 set to 0 with the three-phase motor control timer function pulse output function select bit rw mr2 set to 1 (selected by the trgsr register) with the three-phase motor control timer function trigger select bit mr3 tck1 rw rw rw count source select bit (2) tck0 b7 b6 0 0 : f1timab or f2timab (1) 0 1 : f8timab 1 0 : f32timab 1 1 : fc32 set to 0 with the three-phase motor control timer function notes : 1. write to this register after setting the prc1 bit in the prcr register to 1 (write enabled). 2. if the inv11 bit is 0 (three-phase mode 0) or the inv06 bit is 1 (sawtooth wave modulation mode), set the pwcon bit to 0 (timer b2 underflow). 3. make sure to set the pd8_5 bit to 0 (input) when setting the ivpcr1 bit to 1 (three-phase output forcible cutoff by sd input enabled ). 4. related pins are u(p8_0), u(p8_1), v(p7_2), v(p7_3), w(p7_4), and w(p7_5). if a low-level signal is applied to the p8_5/nmi/sd pin, three-phase motor control timer output is disabled (inv03 = 0). then, the target pins go to a high-impedance state regardless of which functions of those pins are being used. after forced interrupt (cutoff), input ?h? to the p8_5/nmi/sd pin and set the ivpcr1 bit to 0 to cancel the forced cutoff. ? timer b2 special mode register (1) symbol tb2sc address 033eh bit symbol rw pwcon after reset xxxxxx00b rw ? (b7-b2) bit name timer b2 reload timing switch bit function 0 : timer b2 underflow 1 : timer a output at odd-numbered occurrences (2) no register bits. if necessary, set to 0. read as 0 ivpcr1 rw three-phase output port sd control bit 1 (4) 0 : three-phase output forcible cutoff by sd input (high-impedance) disabled 1 : three-phase output forcible cutoff by sd input (high-impedance) enabled (3) b7 b6 b5 b4 b1 b2 b3 b0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 171 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 16. three-phase motor control timer function figure 16.6 registers tb2, trgsr, and tabsr symbol tb2 address 0335h to 0334h after reset indeterminate function rw timer b2 register (1) rw if setting value is n, count source is divided by n+1. timers a1, a2 and a4 start every time an underflow occurs. note : 1. read and write in 16-bit units. setting range 0000h to ffffh b7 b0 b7 b0 (b15) (b8) b7 b6 b5 b4 b1 b2 b3 b0 function bit symbol bit name rw notes : 1. set the corresponding port direction bit to 0 (input mode). 2. overflow or underflow trigger select register symbol trgsr address 0323h after reset 00h a1tgh rw set to 01b (tb2 underflow) before using a v-phase output control circuit timer a1 event / trigger select bit ta1tgl rw ta2tgh rw set to 01b (tb2 underflow) before using a w-phase output control circuit timer a2 event / trigger select bit ta2tgl rw ta3tgh rw rw timer a3 event / trigger select bit ta3tgl b5 b4 0 0 : input on ta3in is selected (1) 0 1 : tb2 is selected (2) 1 0 : ta2 is selected (2) 1 1 : ta4 is selected (2) ta4tgh rw set to 01b (tb2 underflow) before using a u-phase output control circuit timer a4 event / trigger select bit ta4tgl rw b7 b6 b5 b4 b1 b2 b3 symbol tabsr address 0320h after reset 00h b0 function bit symbol bit name rw count start flag 0 : stop counting 1 : start counting tb0s tb2s timer a3 count start flag timer b2 count start flag rw rw rw rw ta4s rw ta3s timer b0 count start flag timer b1 count start flag tb1s timer a4 count start flag timer a1 count start flag ta1s rw timer a2 count start flag rw ta2s timer a0 count start flag ta0s rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 172 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 16. three-phase motor control timer function figure 16.7 registers ta1mr, ta2mr, ta4mr, and tb2mr b7 0 1 0 0 1 0 b6 b5 b4 b1 b2 b3 symbol ta1mr ta2mr ta4mr address 0337h 0338h 033ah after reset 00h 00h 00h b0 function bit symbol bit name rw rw mr1 timer ai mode register (i = 1, 2, 4) tmod1 rw set to 10b (one-shot timer mode) with the three-phase motor control timer function operation mode select bit tmod0 rw set to 0 with the three-phase motor control timer function external trigger select bit notes : 1. selected by the pclk0 bit in the pclkr register. 2. valid when bits tcs3 and tcs7 in registers tacs0 to tacs2 are set to 0. selected by bits tcs2 to tcs0 or tcs6 to tcs4 in registers tacs0 to tacs2 when bits tcs3 and tcs7 are set to 1. (refer to figure 15.8 registers tacs0 and tacs and figure 15.9 tacs2 register ). rw mr0 set to 0 with the three-phase motor control timer function pulse output function select bit rw mr2 set to 1 (selected by the trgsr register) with the three-phase motor control timer function trigger select bit mr3 tck1 rw rw rw count source select bit (2) tck0 b7 b6 0 0 : f1timab or f2timab (1) 0 1 : f8timab 1 0 : f32timab 1 1 : fc32 set to 0 with the three-phase motor control timer function b7 0 0 b6 b5 b4 b1 b2 b3 symbol tb2mr address 033dh after reset 00xx0000b b0 function bit symbol bit name rw mr3 tck1 ? rw rw ? (b4) ro count source select bit (2) tck0 timer b2 mode register b7 b6 0 0 : f1timab or f2timab (1) 0 1 : f8timab 1 0 : f32timab 1 1 : fc32 no register bit. if necessary, set to 0. read as undefined value when write in three-phase motor control timer function, set to 0. read as undefined value in three-phase motor control timer function notes : 1. selected by the pclk0 bit in the pclkr register. 2. valid when the tcs3 bit in the tbcs1 register is set to 0. selected by bits tcs2 to tcs0 in the tbcs1 register when the tcs3 bit in the tbcs1 register is set to 1 (refer to figure 15.21 tbcs1 register ). rw mr1 tmod1 rw rw mr0 set to 00b (timer mode) when using the three-phase motor control timer function operation mode select bit tmod0 rw disabled when using the three-phase motor control timer function. if necessary, set to 0. read as undefined value rej09b0392-0064 rev.0.64 oct 12, 2007 page 173 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 16. three-phase motor control timer function the three-phase motor control timer function is enabled by setting the inv02 bit in the invc0 register to 1. when this function is on, timer b2 is used to contro l the carrier wave, and timers a4, a1, and a2 are used to control three-phase pwm outputs (u, u , v, v , w, and w ). the dead time is controlled by a dedicated dead time timer. figure 16.8 shows an example of triangul ar wave modulation operation and figure 16.9 shows an example of sawtooth wave modulation operation. figure 16.8 example of triangular wave modulation operation triangular waveform as a carrier wave carrier wave signal wave inv00,inv01 : bits in the invc0 register inv11, inv14: bits in the invc1 register notes: 1. internal signals. see figure 16.1 three-phase motor control timer functions block diagram . 2. applies only when the inv11 bit is set to 1 (three-phase mode). (a) when inv11 = 1 (three-phase mode 1) - inv01 = 0 and ictb2 = 2h (timer b2 interrupt is generated with every second timer b2 underflow) or inv01 = 1, inv00 = 1, and ictb2 = 1h (timer b2 interrupt is generated on the falling edge of timer a reload control signal) - default value of the timer: ta41 = m, ta4 = m registers ta4 and ta41 are changed whenever timer b2 interrupt is generated. first time: ta41 = n, ta4 = n. second time: ta41 = p, ta4 = p. - default value of registers idb0 and idb1 du0 = 1, dub0 = 0, du1 = 0, dub1 = 1 they are changed to du0 = 1, dub0 = 0, du1 = 1, dub1 = 0 by the third timer b2 interrupt. tb2s bit in tabsr register timer b2 timer a1 reload control signal (1) timer a4 one-shot pulse (1) u-phase output signal (1) u-phase output signal (1) u-phase u-phase inv14 = 0 (?l? active) u-phase u-phase inv14 = 1 (?h? active) m m nn pp rewritten value is reflected here dead time dead time (b) when inv11 = 0 (three-phase mode 0) - inv01 = 0, ictb2 = 1h (timer b2 interrupt is generated whenever timer b2 underflows) - default value of the timer: ta4 = m the ta4 register is changed whenever timer b2 interrupt is generated. first time: ta4 = m second time: ta4 = n. third time: ta4 = n fourth time: ta = p. fifth time: ta4=p. - default value of registers idb0 and idb1: du0 = 1, dub0 = 0, du1 = 0, dub1 = 1 they are changed to du0 = 1, dub0 = 0, du1 = 1, dub1 = 0 by the sixth timer b2 interrupt. the above applies when invc0 = 00xx11xxb (x varies depending on each system) and invc1 = 010xxxxb. the followings are examples of pwm output change. qq p q p q m m n m n m n n n p p q rewrite registers idb0 and idb1 timer a4 start trigger signal (1) ta4 register (2) ta4-1 register (2) reload register (2) r r q rej09b0392-0064 rev.0.64 oct 12, 2007 page 174 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 16. three-phase motor control timer function figure 16.9 example of sawtooth wave modulation operation sawtooth waveform as a carrier wave carrier wave signal wave inv14: bit in the invc1 register note: 1. see figure 16.1 three-phase motor control timer functions block diagram . timer b2 u-phase output signal (1) u-phase output signal (1) u-phase u-phase inv14 = 0 (?l? active) u-phase u-phase inv14 = 1 (?h? active) rewrite registers idb0 and idb1 rewritten value is reflected here dead time the above applies when invc0 = 01xx110xb (x vari es depending on each system) and invc1 = 010xxx00b the following is an example of pwm output change. - default value of registers idb0 and idb1: du0 = 0, dub0 = 1, du1 = 1, dub1 = 1 they are changed to du0 = 1, dub0 = 0, du1 = 1, dub1 = 1 by the timer b2 interrupt. timer a4 start trigger signal (1) timer a4 one-shot pulse (1) dead time rej09b0392-0064 rev.0.64 oct 12, 2007 page 175 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17. serial interface serial interfaces consist of eight channels: uart 0 to uart2, uart5 to uart7, si/o3, and si/o4. 17.1 uarti (i = 0 to 2, 5 to 7) each uarti has an exclusive timer to generate a tran sfer clock, so it operates independently of each other. figures 17.1 to 17.3 show the block diagrams of ua rti. figure 17.4 shows the uarti transmit / receive unit. uarti has the following modes: ? clock synchronous serial i/o mode ? clock asynchronous seri al i/o mode (uart mode) ? special mode 1 (i 2 c mode) ? special mode 2 ? special mode 3 (bus collision dete ction function, ie mode) ? special mode 4 (sim mode) : uart2 figures 17.5 to 17.11 show the uarti-related registers. refer to tables for each mode for register setting. uart6 and uart7 cannot be used in memory expansion mode or microprocessor mode. rej09b0392-0064 rev.0.64 oct 12, 2007 page 176 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.1 uart0 block diagram figure 17.2 uart1 block diagram n: values set to the u0brg register rxd0 reception control circuit transmission control circuit 1 / (n + 1) 1/16 1/16 1/2 u0brg register clock synchronous type (when internal clock is selected) clock sync type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) clk0 clock source selection cts0 / rts0 f1sio or f2sio f8sio f32sio internal external rts0 cts0 txd0 transmit/ receive unit clk polarity reversing circuit cts / rts disabled cts / rts disabled cts / rts selected receive clock transmit clock txd polarity switching circuit clk1 to clk0 00 01 10 ckdir ckpol uart reception uart transmission clock sync type ckdir 1 0 rxd polarity switching circuit 0 1 cts0 from uart1 rcsp 1 vss 0 1 pclk1 f1sio or f2sio 1/2 f1 1/2 1/8 f8sio 1/4 f32sio f1sio f2sio 0 1 smd2 to smd0 010, 100, 101, 110 001 010, 100, 101, 110 001 0 1 crs 0 crd pclk1 : bit in the pclkr register smd2 to smd0, ckdir : bits in the u0mr register clk1 to clk0, ckpol, crd, crs : bits in the u0c0 register rcsp : bit in the ucon register n: values set to the u1brg register rxd1 reception control circuit transmission control circuit 1 / (n + 1) 1/16 1/16 1/2 u1brg register clock synchronous type (when internal clock is selected) clock sync type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) clk1 clock source selection f1sio or f2sio f8sio f32sio internal external txd1 transmit/ receive unit receive clock transmit clock txd polarity switching circuit clk1 to clk0 00 01 10 ckdir uart reception uart transmission clock sync type ckdir rxd polarity switching circuit 0 1 pclk1 f1sio or f2sio 1/2 f1 1/2 1/8 f8sio 1/4 f32sio f1sio f2sio 0 1 smd2 to smd0 010, 100, 101, 110 001 010, 100, 101, 110 001 0 1 rts1 cts1 clock output pin select cts1 / rts1/ cts0 / clks1 cts / rts disabled cts / rts selected vss cts / rts disabled crd 1 0 0 crs 0 0 1 to cts0 in uart0 clkmd0 1 clk polarity reversing circuit ckpol 1 clkmd1 1 0 rcsp pclk1 : bit in the pclkr register smd2 to smd0, ckdir : bits in the u1mr register clk1 to clk0, ckpol, crd, crs : bits in the u1c0 register clkmd0, clkmd1, rcsp : bits in the ucon register rej09b0392-0064 rev.0.64 oct 12, 2007 page 177 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.3 uart2, and uart 5 to uart7 block diagram note : 1. uart2 is an n-channel open-drain output. cmos output cannot be set. n: values set to the uibrg register i = 2, 5 to 7 rxdi reception control circuit transmission control circuit 1 / (n + 1) 1/16 1/16 1/2 uibrg register clock synchronous type (when internal clock is selected) clock sync type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) clki clock source selection f1sio or f2sio f8sio f32sio internal external rtsi ctsi txdi transmit/ receive unit clk polarity reversing circuit cts / rts disabled cts / rts disabled cts / rts selected receive clock transmit clock txd polarity switching circuit (1) clk1 to clk0 00 01 10 ckdir ckpol uart reception uart transmission clock sync type ckdir 1 0 rxd polarity switching circuit 0 1 vss 0 1 pclk1 f1sio or f2sio 1/2 f1 1/2 1/8 f8sio 1/4 f32sio f1sio f2sio 0 1 smd2 to smd0 010, 100, 101, 110 001 010, 100, 101, 110 001 0 1 crs crd pclk1 : bit in the pclkr register smd2 to smd0, ckdir : bits in the u2mr register clk1 to clk0, ckpol, crd, crs : bits in the u2c0 register ctsi / rtsi rej09b0392-0064 rev.0.64 oct 12, 2007 page 178 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.4 uarti tran smit / receive unit 0 1 0 1 0 1 par disabled par enabled prye 0 1 2sp 1 0 stps 1sp sp sp par uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock sync type clock sync type data bus low-order bits txdi uarti transmit register d8 d7 d6 d5 d4 d3 d2 d1 d0 sp : stop bit par: parity bit i = 0 to 2, 5 to 7 uitb register uart (8 bits) uart (9 bits) clock sync type uirb register uarti receive register sp 1sp par enabled par disabled uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock sync type clock sync type clock sync type rxdi uart (8 bits) uart (9 bits) data bus high-order bits d7 d6 d5 d4 d3 d2 d1 d0 d8 0000000 par reverse no reverse error signal output circuit txd data reverse circuit error signal output enabled error signal output disabled reverse no reverse logic reverse circuit + msb / lsb conversion circuit logic reverse circuit + msb / lsb conversion circuit 0 1 0 1 prye 1 uiere iopol iopol rxd data reverse circuit stps sp 2sp 0 1 0 smd2 to smd0 1 0 1 0 smd2 to smd0 0 1 0 1 i 2 c i 2 c i 2 c i 2 c i 2 c i 2 c smd2 to smd0, stps, prye, iopol, ckdir : bits in the uimr register clk1 to clk0, ckpol, crd, crs : bits in the uic0 register uiere : bit in the uic1 register rej09b0392-0064 rev.0.64 oct 12, 2007 page 179 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.5 registers u0tb to u2tb, u5tb to u7tb, u0rb to u2rb, and u5rb to u7rb symbol address after reset rw uarti transmit buffer register (i = 0 to 2, 5 to 7) (1) u0tb u1tb u2tb u5tb u6tb u7tb 024bh to 024ah 025bh to 025ah 026bh to 026ah 028bh to 028ah 029bh to 029ah 02abh to 02aah indeterminate indeterminate indeterminate indeterminate indeterminate indeterminate wo ? note : 1. use mov instruction to write to this register. function transmit data no register bits. if necessary, set to 0. read as undefined value b7 (b8) b0 b0 (b15) b7 symbol address after reset rw ro uarti receive buffer regist er (i = 0 to 2, 5 to 7) u0rb u1rb u2rb u5rb u6rb u7rb 024fh to 024eh 025fh to 025eh 026fh to 026eh 028fh to 028eh 029fh to 029eh 02afh to 02aeh indeterminate indeterminate indeterminate indeterminate indeterminate indeterminate function bit symbol receive data (d7 to d0) b7 (b8) b0 (b15) b7 b0 ? (b7-b0) ro receive data (d8) ? (b8) ? ? (b10-b9) bit name no register bits. if necessary, set to 0. read as undefined value rw 0 : not detected 1 : detected arbitration lost detect flag (2) abt ro 0 : no overrun error 1 : overrun error found overrun error flag (1) oer ro 0 : no framing error 1 : framing error found framing error flag (1, 3) fer ro 0 : no parity error 1 : parity error found parity error flag (1,3) per ro 0 : no error 1 : error found error sum flag (1, 3) sum notes : 1. when bits smd2 to smd0 in the uimr register = 000b (serial interface disabled) or the re bit in the uic1 register = 0 (reception disabled), all of bits sum, per, fer, and oer are set to 0 (no error). the sum bit is set to 0 (no error) when all of bits per, fer, and oer = 0 (no erro r). bits per and fer are set to 0 by reading the lower byte of the uirb register. 2. the abt bit is set to 0 by writing 0 in a program. (writing a 1 has no effect.) 3. these error flags are disabled when bits smd2 to smd0 are set to 001b (clock synchronous serial i/o mode) or to 010b (i 2 c mode). read as undefined values. rej09b0392-0064 rev.0.64 oct 12, 2007 page 180 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.6 registers u0brg to u2brg, u5brg to u7brg, u0mr to u2mr, and u5mr to u7mr b7 symbol u0brg, u1brg, u2brg u5brg, u6brg, u7brg address 0249h, 0259h, 0269h 0289h, 0299h, 02a9h after reset indeterminate indeterminate b0 function rw uarti bit rate register (i = 0 to 2, 5 to 7) (1, 2, 3) setting range notes : 1. write to this register while seri al interface is neither tr ansmitting nor receiving. 2. use mov instruction to write to this register. 3. write to this register after setting bits clk1 to clk0 in the uic0 register. if set value = n, uibrg divides the count source by n + 1 wo 00h to ffh b7 b6 b5 b4 b1 b2 b3 symbol u0mr, u1mr, u2mr u5mr, u6mr, u7mr address 0248h, 0258h, 0268h 0288h, 0298h, 02a8h after reset 00h 00h b0 function bit symbol bit name rw uarti transmit / receive mode register (i = 0 to 2, 5 to 7) rw stps stop bit length select bit 0 : 1 stop bit 1 : 2 stop bits rw ckdir internal / external clock select bit 0 : internal clock 1 : external clock (1) note : 1. set the corresponding port direction bit for each clki pin to 0 (input mode). 2. to receive data, set the corresponding port direction bit for each rxdi pin to 0 (input mode). 3. set the corresponding port direction bit for pins scl and sda to 0 (input mode). rw pry odd / even parity select bit valid when prye = 1 0 : odd parity 1 : even parity rw iopol txd, rxd i/o polarity reverse bit 0 : no reverse 1 : reverse rw prye parity enable bit 0 : parity disabled 1 : parity enabled smd0 smd1 smd2 rw rw rw serial i/o mode select bit b2 b1 b0 0 0 0 : serial interface disabled 0 0 1 : clock synchronous serial i/o mode 0 1 0 : i 2 c mode (3) 1 0 0 : uart mode transfer data 7 bits long 1 0 1 : uart mode transfer data 8 bits long 1 1 0 : uart mode transfer data 9 bits long do not set except above rej09b0392-0064 rev.0.64 oct 12, 2007 page 181 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.7 registers u0c0 to u2c0 and u5c0 to u7c0 b7 b6 b5 b4 b1 b2 b3 symbol u0c0, u1c0, u2c0 u5c0, u6c0, u7c0 address 024ch, 025ch, 026ch 028ch, 029ch, 02ach after reset 00001000b 00001000b b0 function bit symbol bit name rw crs clk1 clk0 uibrg count source select bit (6) uarti transmit / receive control r egister 0 (i = 0 to 2, 5 to 7) rw rw rw cts / rts function select bit (4) valid when crd = 0 0 : cts function selected (1) 1 : rts function selected b1 b0 0 0 : f1sio or f2sio is selected (5) 0 1 : f8sio is selected 1 0 : f32sio is selected 1 1 : do not set to this value notes : 1. set the corresponding port direction bit for each ctsi pin to 0 (input mode). 2. txd2 / sda2 and scl2 are n-channel open-drain output. cannot be set to the cmos output. no nch bit in the u2c0 register is assigned. if necessary, set to 0. 3. the uform bit is enabled when bits smd2 to smd0 in the uimr register are set to 001b (clock synchronous serial i/o mode), or 101b (uart mode, 8-bit transfer data). set this bit to 1 when bits smd2 to smd0 are set to 010b (i 2 c mode), and to 0 when bits smd2 to smd0 are set to 100b (uart mode, 7-bit transfer data) or 110b (uart mode, 9-bit transfer data). 4. cts1 / rts1 can be used when the clkmd1 bit in the ucon register = 0 (only clk1 output) and the rcsp bit in the ucon register = 0 (cts0 / rts0 not separated). 5. selected by the pclk1 bit in the pclkr register. 6. when changing bits clk1 and clk0, set the uibrg register. crd 0 : cts / rts function enabled 1 : cts / rts function disabled (p6_0, p6_4, p7_3, p8_1, p1_0, and p4_4 can be used as i/o ports) cts / rts disable bit rw 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) transmit register empty flag txept ro rw nch 0 : pins txdi / sdai and scli are cmos output 1 : pins txdi / sdai and scli are n- channel open-drain output data output select bit (2) rw ckpol clk polarity select bit 0 : transmit data is output at the falling edge of transfer clock and receive data is input at the rising edge 1 : transmit data is output at the rising edge of transfer clock and receive data is input at the falling edge transfer format select bit (3) 0 : lsb first 1 : msb first uform rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 182 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.8 registers u0c1 to u2c1 and u5c1 to u7c1 symbol u0c1, u1c1 address 024dh, 025dh after reset 00xx0010b function bit symbol bit name rw re ti te uilch 0 : data present in uirb register 1 : no data present in uirb register receive complete flag transmit enable bit ri 0 : no reverse 1 : reverse data logic select bit (1) uarti transmit / receive control register 1 (i = 0, 1) rw ro rw ro rw receive enable bit 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled note : 1. the uilch bit enabled when bits smd2 to smd0 in the uimr register are set to 001b (clock sychronous serial i/ o mode), 100b (uart mode, 7-bit transf er data), or 101b (uart mode, 8-bit transfer data) . set this bit to 0 when bits smd2 to smd0 are set to 010b (i 2 c mode) or 110b (uart mode, 9-bit transfer data). transmit buffer empty flag 0 : data present in uitb register 1 : no data present in uitb register uiere error signal output enable bit 0 : output disabled 1 : output enabled rw no register bits. if necessary, set to 0. read as undefined value ? (b5-b4) ? b7 b6 b5 b4 b1 b2 b3 b0 b7 b6 b5 b4 b1 b2 b3 symbol u2c1 u5c1, u6c1, u7c1 address 026dh 028dh, 029dh, 02adh after reset 00000010b 00000010b b0 function bit symbol bit name rw re ti te uirrm 0 : no data present in uirb register 1 : data present in uirb register receive complete flag transmit enable bit uilrs ri 0 : uitb register empty (ti = 1) 1 : transmit completed (txept = 1) uarti transmit interrupt source select bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled uarti continuous receive mode enable bit uarti transmit / receive control register 1 (i = 2, 5 to 7) rw ro rw ro rw rw receive enable bit 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled note : 1. the uilch bit is enabled when bits smd2 to sm d0 in the uimr regi ster are set to 001b (clock synchronous serial i/o mode), 100b (uart mode, 7-bit transfer data), or 101b (uart mode, 8-bit transfer data). set this bit to 0 when bits smd2 to smd0 are set to 010b (i 2 c mode) or 110b (uart mode, 9-bit transfer data). transmit buffer empty flag 0 : data present in uitb register 1 : no data present in uitb register uilch data logic select bit (1) 0 : no reverse 1 : reverse rw uiere error signal output enable bit 0 : output disabled 1 : output enabled rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 183 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.9 registers ucon, u0smr to u2smr, and u5smr to u7smr symbol ucon address 0250h after reset x0000000b function bit symbol bit name rw u0rrm u1irs u0irs clkmd1 0 : continuous receive mode disabled 1 : continuous receive mode enabled uart1 continuous receive mode enable bit uart0 transmit interrupt source select bit u1rrm 0 : clk output is only from clk1 1 : transfer clock output from multiple-pin output function selected uart1clk, clks select bit 1 (1) uart transmit / receive control register 2 rw rw rw rw rw uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) note : 1. when using multiple transfer clock output pins, make sure the following conditions are met: the ckdir bit in the u1mr register = 0 (internal clock) uart1 transmit interrupt source select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) rcsp separate uart0 cts / rts bit 0 : cts / rts shared pin 1 : cts / rts separated (cts0 supplied from the p6_4 pin) rw ? (b7) no register bit. if necessary, set to 0. read as undefined value ? clkmd0 valid when clkmd1 = 1 0 : clock output from clk1 1 : clock output from clks1 uart1clk, clks select bit 0 rw b7 b6 b5 b4 b1 b2 b3 b0 symbol u0smr, u1smr, u2smr u5smr, u6smr, u7smr address 0247h, 0257h, 0267h 0287h, 0297h, 02a7h after reset x0000000b x0000000b function bit symbol bit name rw bbs abc iicm acse set to 0 reserved bit i 2 c mode select bit ? (b3) 0 : no auto clear function 1 : auto clear at occurrence of bus collision auto clear function select bit of transmit enable bit uarti special mode register (i = 0 to 2, 5 to 7) rw rw rw rw rw bus busy flag (1) 0 : stop-condition detected 1 : start-condition detected (busy) 0 : other than i 2 c mode 1 : i 2 c mode arbitration lost detect flag control bit 0 : update per bit 1 : update per byte sss transmit start condition select bit 0 : not synchronized to rxdi 1 : synchronized to rxdi (3) rw ? (b7) no register bit. if necessary, set to 0. read as undefined value ? abscs 0 : rising edge of transfer clock 1 : underflow signal of timer aj (2) bus collision detect sampling clock select bit rw b7 0 b6 b5 b4 b1 b2 b3 b0 notes : 1. the bbs bit is set to 0 by writing a 0 in a program (writing a 1 has no effect). 2. underflow signal of timer a3 in uart0 and uart6, underflow signal of timer a4 in uart1 and uart7, and underflow signal of timer a0 in uart2 and uart5 3. when a transfer begins, the sss bit is set to 0 (not synchronized to rxdi). rej09b0392-0064 rev.0.64 oct 12, 2007 page 184 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.10 registers u0smr2 to u2smr2, u5smr2 to u7sm r2, u0smr3 to u2smr3, and u5smr3 to u7smr3 symbol u0smr2, u1smr2, u2smr2 u5smr2, u6smr2, u7smr2 address 0246h, 0256h, 0266h 0286h,0296h,02a6h after reset x0000000b x0000000b function bit symbol bit name rw swc csc iicm2 swc2 0 : disabled 1 : enabled sda output stop bit i 2 c mode select bit 2 als 0: transfer clock 1: ?l? output scl wait output bit 2 uarti special mode register 2 (i = 0 to 2, 5 to 7) rw rw rw rw rw scl wait output bit 0 : disabled 1 : enabled see table 17.13 i 2 c mode functions clock synchronization bit 0 : disabled 1 : enabled sdhi sda output disable bit 0: enabled 1: disabled (high-impedance) rw ? (b7) no register bit. if necessary, set to 0. read as undefined value ? stac 0 : disabled 1 : enabled uarti initialization bit rw b7 b6 b5 b4 b1 b2 b3 b0 b7 b6 b5 b4 b1 b2 b3 symbol u0smr3, u1smr3, u2smr3 u5smr3, u6smr3, u7smr3 address 0245h, 0255h, 0265h 0285h, 0295h, 02a5h after reset 000x0x0xb 000x0x0xb b0 function bit symbol bit name rw uarti special mode register 3 (i = 0 to 2, 5 to 7) notes : 1. bits dl2 to dl0 are used to generate a delay in sdai output by digital means during i 2 c mode. in other than i 2 c mode, set these bits to 000b (no delay). 2. the amount of delay varies with the load on pins scli and sdai. also, when using an external clock, the amount of delay increases by about 100 ns. dl1 rw dl0 sdai digital delay setup bit (1, 2) b7 b6 b5 0 0 0 : without delay 0 0 1 : 1 to 2 cycle(s) of uibrg count source 0 1 0 : 2 to 3 cycles of uibrg count source 0 1 1 : 3 to 4 cycles of uibrg count source 1 0 0 : 4 to 5 cycles of uibrg count source 1 0 1 : 5 to 6 cycles of uibrg count source 1 1 0 : 6 to 7 cycles of uibrg count source 1 1 1 : 7 to 8 cycles of uibrg count source ? (b0) ? no register bit. if necessary, set to 0. read as undefined value rw ckph clock phase set bit 0 : without clock delay 1 : with clock delay ? (b2) ? no register bit. if necessary, set to 0. read as undefined value rw nodc clock output select bit 0 : clki is cmos output 1 : clki is n-channel open drain output dl2 rw rw ? (b4) ? no register bit. if necessary, set to 0. read as undefined value rej09b0392-0064 rev.0.64 oct 12, 2007 page 185 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.11 registers u0smr4 to u2smr4 and u5smr4 to u7smr4 symbol u0smr4, u1smr4, u2smr4 u5smr4, u6smr4, u7smr4 address 0244h, 0254h, 0264h 0284h, 0294h, 02a4h after reset 00h 00h function bit symbol bit name rw stpreq rstareq stareq ackc start condition generate bit (1) 0 : serial interface data output 1 : ack data output ack data output enable bit uarti special mode register 4 (i = 0 to 2, 5 to 7) rw rw rw rw stop condition generate bit (1) 0 : clear 1 : start 0 : clear 1 : start restart condition generate bit (1) 0 : clear 1 : start sclhi scl output stop enable bit 0 : disabled 1 : enabled rw swc9 rw ackd 0 : ack 1 : nack ack data bit rw b7 b6 b5 b4 b1 b2 b3 b0 scl wait bit 3 0 : scl ?l? hold disabled 1 : scl ?l? hold enabled note : 1. set to 0 when each condition is generated. 0 : start and stop conditions not output 1 : start and stop conditions output scl, sda output select bit stspsel rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 186 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.1 clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. table 17.1 lists the clock synchronous serial i/o mode specifications. table 17.2 lists registers to be used and set- tings in clock synchronous serial i/o mode. i = 0 to 2, 5 to 7 notes: 1. when an external clock is selected, the conditions must be met while if th e ckpol bit in the uic0 register = 0 (transmit data output at the falling edge and the receive data take n in at the rising edge of the transfer clock), the external clock is in the high state; if the ckpol bit in the uic0 register = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. 2. if an overrun er ror occurs, the receive data of the uirb re gister will be indetermi nate. the ir bit in the siric register does not chan ge to 1 (interrupt requested). 3. bits u0irs and u1irs correspond to bits 0 and 1 in the ucon register respectively. bits u2irs, table 17.1 clock synchronous serial i/o mode specifications item specification transfer data format transfer data length: 8 bits transfer clock ? ckdir bit in the uimr register = 0 (internal clock): fj / (2(n+1)) fj = f1sio, f2sio, f8sio, f32sio n = sett ing value of uibrg register 00h to ffh ? ckdir bit = 1 (external clock) : input from clki pin transmission, reception control selectable from cts function, rts function or cts / rts function disable transmission start condition before transmission starts, satisfy the following requirements (1) ? the te bit in the uic1 register = 1 (transmission enabled) ? the ti bit in the uic1 register = 0 (data present in uitb register) ?if cts function is selected, input on the ctsi pin = ?l? reception start condition before reception starts, satisfy the following requirements (1) ? the re bit in the uic1 register = 1 (reception enabled) ? the te bit in the uic1 register = 1 (transmission enabled) ? the ti bit in the uic1 register = 0 (dat a present and dummy written in the uitb reg- ister) interrupt request generation timing for transmission, one of the following conditions can be selected ? the uiirs bit (3) = 0 (transmit buffer empty): when transferring data from the uitb register to the uarti transmit r egister (at start of transmission) ? the uiirs bit =1 (transfer completed): when the serial interface finished sending data from the uarti transmit register for reception ? when transferring data from the uarti receive register to the uirb register (at com- pletion of reception) error detection overrun error (2) this error occurs if the serial interface started receiving the next data before reading the uirb register and received the 7th bit of the next data select function ? clk polarity selection transfer data input / output can be chosen to occur synchronously with the rising or the falling edge of the transfer clock ? lsb first, msb first selection whether to start sending / receiving data beginning with bit 0 or beginning with bit 7 can be selected ? continuous receive mode selection reception is enabled immediately by reading the uirb register ? switching serial data logic this function reverses the logic value of the transmit / receive data ? transfer clock output from mu ltiple pins selection (uart1) the output pin can be selected in a program from two uart1 transfer clock pins that have been set ? separate cts / rts pins (uart0) cts0 and rts0 are input / output from separate pins rej09b0392-0064 rev.0.64 oct 12, 2007 page 187 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface u5irs, u6irs, and u7irs are in registers u2c1, u5c1, u6c1, and u7c1 respectively. i = 0 to 2, 5 to 7 notes: 1. set bits 4 and 5 in registers u0c1 and u1c1 to 0. bits u0irs, u1irs, u0rrm, and u1rrm are in the ucon register. 2. the txd2 pin is n channel open-drain output . set the nch bit in the u2c0 register to 0. 3. set bits not listed above to 0 when writing to th e registers in clock synchronous serial i/o mode. table 17.2 registers to be used and settings in clock synchronous serial i/o mode register bit function uitb (3) 0 to 7 set transmission data uirb (3) 0 to 7 reception data can be read oer overrun error flag uibrg 0 to 7 set a bit rate uimr (3) smd2 to smd0 set to 001b ckdir select the internal clock or external clock iopol set to 0 uic0 clk1 to clk0 select the count source for the uibrg register crs select either cts or rts to use functions txept transmit register empty flag crd enable or disable the cts or rts function nch select txdi pin output mode (2) ckpol select the transfer clock polarity uform select the lsb first or msb first uic1 te set this bit to 1 to enable transmission / reception ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag uiirs (1) select the source of uarti transmit interrupt uirrm (1) set this bit to 1 to use continuous reception mode uilch set this bit to 1 to use inverted data logic uiere set to 0 uismr 0 to 7 set to 0 uismr2 0 to 7 set to 0 uismr3 0 to 2 set to 0 nodc select clock output mode 4 to 7 set to 0 uismr4 0 to 7 set to 0 ucon u0irs, u1irs select the source of uart0 / uart1 transmit interrupt u0rrm, u1rrm set this bit to 1 to use continuous reception mode clkmd0 select the transfer clock output pin when clkmd1 = 1 clkmd1 set this bit to 1 to output uart1 transfer clock from two pins rcsp set this bit to 1 to accept as input the cts0 signal of uart0 from the p6_4 pin 7 set to 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 188 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface table 17.3 lists the functions of the input / output pins during clock synchronous serial i/o mode. table 17.3 shows pin functions for the case where the multip le transfer clock output pin select function is not selected. table 17.4 lists the p6_4 pin functions during clock synchronous serial i/o mode. note that for a period from when uarti operating mode is selected to when transfer starts, the txdi pin outputs ?h? (if the n-channel open-drain output is selected, this pin is in high-impedance state). i = 0 to 2, 5 to 7 - indicates either 0 or 1 notes: 1. in addition to this, set the crd bit in the u0c0 register to 0 ( cts0 / rts0 enabled) and the crs bit in the u0c0 register to 1 ( rts0 selected). 2. when the clkmd1 bit = 1 and the clkmd0 bit = 0, the following logic levels are output: ? high if the clkpol bit in the u1c0 register = 0 ? low if the clkpol bit in the u1c0 register = 1 table 17.3 pin functions during clock synchronous serial i/o mode (multiple transfer clock output pin function not selected) pin name function method of selection txdi serial data output (outputs dummy data when performing reception only) rxdi serial data input set the port direction bit corresponding to the rxdi pin = 0 (can be used as an input port when performing transmission only) clki transfer clock output the ckdir bit in the uimr register = 0 transfer clock input the ckdir bit in the uimr register = 1 set the port direction bit corresponding to the clki pin = 0 ctsi / rtsi cts input the crd bit in the uic0 register = 0 the crs bit in the uic0 register = 0 set the port direction bit corresponding to the ctsi pin = 0 rts output the crd bit in the uic0 register = 0 the crs bit in the uic0 register = 1 i/o port the crd bit in the uic0 register = 1 table 17.4 p6_4 pin functions durin g clock synchronous serial i/o mode pin function bit set value u1c0 register ucon register pd6 register crd crs rcsp clkmd1 clkmd0 pd6_4 p6_4 1 - 0 0 - input: 0, output: 1 cts1 0000- 0 rts1 0100- - cts0 (1) 0010- 0 clks1 - - - 1 (2) 1- rej09b0392-0064 rev.0.64 oct 12, 2007 page 189 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.12 transmit and receive operation during clock synchronous serial i/o mode d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 tc t clk pulse stops because the te bit is set to 0 data is set in the uitb register data is transferred from the uitb register to the uarti transmit register t c = t clk = 2(n + 1) / fj fj: frequency of uibrg count source (f1sio, f2sio, f8sio, f32sio) n: value set to the uibrg register transfer clock te bit in uic1 register ti bit in uic1 register clk i txdi txept flag in uic0 register ?h? ?l? ?0? ?1? ?0? ?1? ?0? ?1? ctsi ir bit in sitic register ?0? ?1? set to 0 by an interrupt request acknowledgement or by program pulse stops because an "h? signal is applied to ctsi 1 / fext dummy data is set in the uitb register clki rxdi rtsi ?h? ?l? ?0? ?1? ?0? ?1? ?0? ?1? re bit in uic1 register ?0? ?1? data is transferred from the uitb register to the uarti transmit register read by the uirb register fext: frequency of the external clock make sure the following conditions are met when input to the clki pin before receiving data is high: the te bit in the uic0 register = 1 (transmit enabled) the re bit in the uic1 register = 1 (receive enabled) write dummy data to the uitb register data is transferred from the uarti receive register to the uirb register ?0? ?1? set to 0 by an interrupt request acknowledgement or by program d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d0 d1 d2 d3 d4 d5 d7 d6 ?0? ?1? d6 te bit in uic1 register ti bit in uic1 register oer flag in uirb register ir bit in siric register ri bit in uic1 register the above timing diagram applies to the case where the register bits are set as follows: the ckdir bit in the uimr register = 0 (internal clock) the crd bit in the uic0 register = 0 (cts / rts enabled), the crs bit = 0 (cts selected) the ckpol bit in the uic0 register = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) the uiirs bit in the uic1 register = 0 (an interrupt request occurs when the uitb register becomes empty) the above timing diagram applies to the case where the register bits are set as follows: the ckdir bit in the uimr register = 1 (external clock) the crd bit in the uic0 register = 0 (cts / rts enabled), the crs bit = 1 (rts selected) the ckpol bit in the uic0 register = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) i = 0 to 2, 5 to 7 received data is taken in an "l? signal is applied when the uirb register is read i = 0 to 2, 5 to 7 (1) example of transmit timing (when internal clock is selected) (2) example of receive timing (when external clock is selected) rej09b0392-0064 rev.0.64 oct 12, 2007 page 190 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.1.1 counter measure fo r communication error if a communication error occurs while transmitting or receiving in clock synchronous serial i/o mode, follow the procedures below. ? resetting the uirb register (i = 0 to 2, 5 to 7) (1) set the re bit in the uic1 register to 0 (reception disabled) (2) set bits smd2 to smd0 in the uimr register to 000b (serial interface disabled) (3) set bits smd2 to smd0 in the uimr register to 001b (clock synchronous serial i/o mode) (4) set the re bit in the uic1 register to 1 (reception enabled) ? resetting the uitb register (i = 0 to 2, 5 to 7) (1) set bits smd2 to smd0 in the uimr register to 000b (serial interface disabled) (2) set bits smd2 to smd0 in the uimr register to 001b (clock synchronous serial i/o mode) (3) a 1 is written to the re bit in the uic1 regist er (transmission enabled), regardless of the value of the te bit in the uici register 17.1.1.2 clk polarity select function use the ckpol bit in the uic0 register (i = 0 to 2, 5 to 7) to select the transfer clock polarity. figure 17.13 shows the transfer clock polarity. figure 17.13 transfer clock polarity (2) when the ckpol bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock) d1 d2 d3 d4 d5 d6 d7 d1 d2 d3 d4 d5 d6 d7 d0 d0 txdi rxdi clki (1) when the ckpol bit in the uic0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 txdi rxdi clki the above applies to the case where the uform bit in the uic0 register = 0 (lsb first) and the uilch bit in the uic1 register = 0 (no reverse). i = 0 to 2, 5 to 7 ?h? is output from the clki pin during no transmission. ?l? is output from the clki pin during no transmission. rej09b0392-0064 rev.0.64 oct 12, 2007 page 191 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.1.3 lsb first / msb first select function use the uform bit in the uic0 register (i = 0 to 2, 5 to 7) to select the transfer format. figure 17.14 shows the transfer format. figure 17.14 transfer format 17.1.1.4 continuous reception mode in continuous reception mode, receive operation becomes enabled when the receive buffer register is read. it is not necessary to write dummy data into the transmit buffer register to enable receive operation in this mode. however, a dummy read of the receive buffer register is required when start- ing the operating mode. when the uirrm bit (i = 0 to 2, 5 to 7) = 1 (contin uous reception mode), the ti bit in the uic1 register is set to 0 (data present in the uitb register) by reading the uirb register. in this case, i.e., uirrm bit = 1, do not write dummy data to the uitb r egister in a program. bits u0rrm and u1rrm corre- spond to bits 2 and 3 in the ucon register , respectively. bits u2rrm, u5rrm, u6rrm, and u7rrm are in registers u2 c1, u5c1, u6c1, and u7c1. (1) when the uform bit in the uic0 register = 0 (lsb first) d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 txdi rxdi clki (2) when the uform bit in the uic0 register = 1 (msb first) d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 txdi rxdi clki the above applies to the case where the ckpol bit in the uic0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), and the uilch bit in the uic1 register = 0 (no reverse). i = 0 to 2, 5 to 7 rej09b0392-0064 rev.0.64 oct 12, 2007 page 192 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.1.5 serial data l ogic switching function when the uilch bit in the uic1 register (i = 0 to 2, 5 to 7) = 1 (reverse), the data written to the uitb register has its logic reversed before being transmi tted. similarly, the received data has its logic reversed when read from the uirb register. fi gure 17.15 shows serial data logic switching. figure 17.15 serial data logic switching 17.1.1.6 transfer clock output from multiple pins (uart1) use bits clkmd1 to clkmd0 in the ucon register to select one of the two transfer clock output pins (see figure 17.16 ). this function can be used when the selected transfer clock for uart1 is an internal clock. figure 17.16 transfer clock output from multiple pins d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txdi (no reverse) (1) when the uilch bit in the uic1 register = 0 (no reverse) (2) when the uilch bit in the uic1 register = 1 (reverse) this applies to the case where the ckpol bit in the uic0 register = 0 (transmit data output at the falling edge of the transfer clock), and the uform bit in the uic0 register = 0 (lsb first) i = 0 to 2, 5 to 7 ?l? ?h? ?l? d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txdi (reverse) ?h? ?l? ?h? ?l? ?h? microcomputer txd1 (p6_7) clks1 (p6_4) clk1 (p6_5) in clk in clk transfer enabled when the clkmd0 bit in the ucon register = 0 transfer enabled when the clkmd0 bit in the ucon register = 1 the above applies to the case where the ckdir bit in the u1mr register = 0 (internal clock) and the clkmd1 bit in the ucon register = 1 (transfer clock output from multiple pins). rej09b0392-0064 rev.0.64 oct 12, 2007 page 193 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.1.7 cts / rts function the cts function is used to start transmit and receive operation when ?l? is applied to the ctsi / rtsi (i = 0 to 2, 5 to 7) pin. transmit and receive operation begins when the ctsi / rtsi pin is held ?l?. if the ?l? signal is switched to ?h? during a transmit or receive operation, the operation stops before the next data. for the rts function, the ctsi / rtsi pin outputs ?l? when the microc omputer is ready to receive. the output level becomes ?h? on the first falling edge of the clki pin. ? the crd bit in the uic0 register = 1 (disable cts / rts function) ctsi / rtsi pin is programmable i/o function ? the crd bit = 0, crs bit = 0 ( cts function selected) ctsi / rtsi pin is cts function ? the crd bit = 0, crs bit = 1 ( rts function selected) ctsi / rtsi pin is rts function 17.1.1.8 cts / rts separate function (uart0) this function separates cts0 / rts0 , outputs rts0 from the p6_0 pin, and inputs cts0 from the p6_4 pin. to use this function, set the register bits as shown below. ? the crd bit in the u0c0 register = 0 (enable cts / rts of uart0) ? the crs bit in the u0c0 register = 1 (output rts of uart0) ? the crd bit in the u1c0 register = 0 (enable cts / rts of uart1) ? the crs bit in the u1c0 register = 0 (input cts of uart1) ? the rcsp bit in the ucon register = 1 (inputs cts0 from the p6_4 pin) ? the clkmd1 bit in the ucon register = 0 (clks1 not used) note that when using the cts / rts separate function, cts / rts of uart1 function cannot be used. figure 17.17 cts / rts separate function microcomputer txd0 (p6_3) rxd0 (p6_2) in out cts rts cts0 (p6_4) rts0 (p6_0) ic clk0 (p6_1) clk rej09b0392-0064 rev.0.64 oct 12, 2007 page 194 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.2 clock asynchronous se rial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. table 17.5 lists the uart mode specifications. i = 0 to 2, 5 to 7 notes: 1. if an overrun error occurs, the receive data of the uirb re gister will be indeterminate. the ir bit in the siric reg- ister does not change. 2. bits u0irs and u1irs are bits 0 and 1 in the ucon register. bits u2irs, u5irs, u6irs, and u7irs are in reg- isters u2c1, u5c1, u6c1, and u7c1. 3. the timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the uarti receive register to the uirb register. table 17.5 uart mode specifications item specification transfer data format ? character bit (transfer data): selectable from 7, 8, or 9 bits ? start bit : 1 bit ? parity bit : selectable from odd, even, or none ? stop bit : selectable from 1 bit or 2 bits transfer clock ? the ckdir bit in the uimr register = 0 (internal clock): fj / (16(n + 1)) fj = f1sio, f2sio, f8sio, f32sio n: setting value of uibrg register 00h to ffh ? ckdir bit = 1 (external clock): fext / (16(n + 1)) fext: input from clki pin n: setting value of uibrg register 00h to ffh transmission, reception control selectable from cts function, rts function or cts / rts function disabled transmission start condition before transmissi on starts, satisfy the following requirements ? the te bit in the uic1 register = 1 (transmission enabled) ? the ti bit in the uic1 register = 0 (data present in the uitb register) ?if cts function is selected, input on the ctsi pin = ?l? reception start condition before reception starts, satisfy the following requirements ? the re bit in the uic1 register = 1 (reception enabled) ? start bit detection interrupt request generation timing for transmission, one of the following conditions can be selected ? the uiirs bit (2) = 0 (transmit buffer empty): when transferring data from the uitb register to the uarti transmit register (at start of transmission) ? the uiirs bit =1 (transfer completed): when the serial interface completes sending data from the uarti transmit register for reception ? when transferring data from the uarti receive register to the uirb register (at com- pletion of reception) error detection ? ov errun error (1) this error occurs if the serial interface started receiving the next data before reading the uirb register and received the bit one before the last stop bit of the next data ? framing error (3) this error occurs when the number of stop bits set is not detected ? parity error (3) this error occurs when if parity is enabled, the number of 1 in parity and character bits does not match the number of 1 set ? error sum flag this flag is set to 1 when any of the overrun, framing, or parity errors occur select function ? lsb first, msb first selection whether to start sending / receiving data beginning with bit 0 or beginning with bit 7 can be selected ? serial data logic switch this function reverses the logic of the transmit / receive data. the start and stop bits are not reversed. ? txd, rxd i/o polarity switch this function reverses the polarities of the txd pin output and rxd pin input. the logic levels of all i/o data are reversed. ? separate cts / rts pins (uart0) cts0 and rts0 are input / output from separate pins. rej09b0392-0064 rev.0.64 oct 12, 2007 page 195 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface i = 0 to 2, 5 to 7 notes: 1. the bits used for transmit / receive data are as follows : bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long. 2. set the bit 4 and bit 5 in registers u0c1 and u1c1 to 0. bits u0irs, u1irs, u0rrm, and u1rrm are included in the ucon register. 3. txd2 pin is n channel open-drain output. set the nch bit in the u2c0 register to 0. table 17.6 registers to be used and settings in uart mode register bit function uitb 0 to 8 set transmission data (1) uirb 0 to 8 reception data can be read (1) oer, fer, per, sum error flag uibrg 0 to 7 set a bit rate uimr smd2 to smd0 set these bits to 100b when transfer data is 7 bits long set these bits to 101b when transfer data is 8 bits long set these bits to 110b when transfer data is 9 bits long ckdir select the internal clock or external clock stps select the stop bit pry, prye select whether parity is included and whether odd or even iopol select the txd / rxd input / output polarity uic0 clk0, clk1 select the count source for the uibrg register crs select cts or rts to use functions txept transmit register empty flag crd enable or disable the cts or rts function nch select txdi pin output mode (3) ckpol set to 0 uform lsb first or msb first can be selected when transfer data is 8 bits long. set this bit to 0 when transfer data is 7 or 9 bits long. uic1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag uiirs (2) select the source of uarti transmit interrupt uirrm (2) set to 0 uilch set this bit to 1 to use reversed data logic uiere set to 0 uismr 0 to 7 set to 0 uismr2 0 to 7 set to 0 uismr3 0 to 7 set to 0 uismr4 0 to 7 set to 0 ucon u0irs, u1irs select the source of uart0 / uart1 transmit interrupt u0rrm, u1rrm set to 0 clkmd0 invalid because clkmd1 = 0 clkmd1 set to 0 rcsp set this bit to 1 to accept as input cts0 signal of uart0 from the p6_4 pin 7 set to 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 196 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface table 17.7 lists the functions of the input / output pins during uart mode. table 17.8 lists the p6_4 pin functions in uart mode. note that for a peri od from when the uarti operating mode is selected to when transfer starts, the txdi pin outputs ?h? (if t he n-channel open-drain output is selected, this pin is in high-impedance state). i = 0 to 2 , 5 to 7 ? indicates either 0 or1. note: 1. in addition to this, set the crd bit in the u0c0 register to 0 ( cts0 / rts0 enabled) and the crs bit in the u0c0 register to 1 ( rts0 selected). table 17.7 i/o pin functions in uart mode pin name function method of selection txdi serial data output (?h? output when performing reception only) rxdi serial data input set the port direction bit corresponding to the rxdi pin to 0 (can be used as an input port when performing transmission only) clki input / output port the ckdir bit in the uimr register = 0 transfer clock input the ckdir bit in the uimr register = 1 set the port direction bit corresponding to the clki pin to 0 ctsi / rtsi cts input the crd bit in the uic0 register = 0 the crs bit in the uic0 register = 0 set the port direction bit corresponding to the ctsi pin to 0 rts input the crd bit in the uic0 register = 0 the crs bit in the uic0 register = 1 input / output port the crd bit in the uic0 register = 1 table 17.8 p6_4 pin fun ctions in uart mode pin function bit set value u1c0 register ucon register pd6 register crd crs rcsp clkmd1 pd6_4 p6_4 1 - 0 0 input: 0, output: 1 cts1 00000 rts1 0100- cts0 (1) 00100 rej09b0392-0064 rev.0.64 oct 12, 2007 page 197 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.18 transmit timing in uart mode d0 d1 d2 d3 d4 d5 d6 d7 st p parity bit txdi ctsi the above timing diagram applies to the case where the register bits are set as follows: the prye bit in the uimr register = 1 (parity enabled) the stps bit in the uimr register = 0 (1 stop bit) the crd bit in the uic0 register = 0 (cts / rts enabled) and the crs bit = 0 (cts selected) the uiirs bit in the uic1 register = 1 (an interrupt request occurs when transmit completed) ?0? ?1? ?0? ?1? ?h? ?0? ?1? tc = 16 (n + 1) / fj or 16 (n + 1) / fext fj : frequency of uibrg count source (f1sio, f2sio, f8sio, f32sio) fext : frequency of uibrg count source (external clock) n : value set to uibrg ?0? ?1? set to 0 by an interrupt reques t acknowledgement or by program d0 d1 d2 d3 d4 d5 d6 d7 st p d0 d1 st txdi ?0? ?1? ?0? ?1? ?0? ?1? the above timing diagram applies to the case where the register bits are set as follows: the prye bit in the uimr register = 0 (parity disabled) the stps bit in the uimr register = 1 (2 stop bits) the crd bit in the uic0 register = 1 (cts / rts disabled) the uiirs bit in the uic1 register = 0 (an interrupt request occurs when transmit buffer becomes empty) transfer clock tc ?0? ?1? set to 0 by an interrupt reques t acknowledgement or by program tc transfer clock stop bit data is set in the uitb register data is transferred from the uitb register to the uarti transmit register start bit d0 d1 d2 d3 d4 d5 d6 d7 st d8 d0 d1 d2 d3 d4 d5 d6 d7 st d8 d0 d1 st sp sp stop bit the transfer clock stops once because an ?h ? signal is applied to the cts pin when the stop bit is verified. the transfer clock resumes running as soon as an ?l? signal is applied to the cts pin. data is set in the uitb register sp data is transferred from the uitb register to the uarti transmit register stop bit te bit in uic1 register ti bit in uic1 register txept bit in uic0 register ir bit in sitic register te bit in uic1 register ti bit in uic1 register txept bit in uic0 register ir bit in sitic register i = 0 to 2, 5 to 7 i = 0 to 2, 5 to 7 ?l? pulse stops because the te bit is set to 0 sp sp start bit sp tc = 16 (n + 1) / fj or 16 (n + 1) / fext fj : frequency of uibrg count source (f1sio, f2sio, f8sio, f32sio) fext: frequency of uibrg count source (external clock) n : value set to uibrg (1) 8-bit data transmit timing (with a parity and 1 stop bit) (2) 9-bit data transmit timing (with no parity and 2 stop bits) rej09b0392-0064 rev.0.64 oct 12, 2007 page 198 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.19 receive timing in uart mod 17.1.2.1 bit rate in uart mode, the frequency set by the uibrg register (i = 0 to 2, 5 to 7) divided by 16 become bit rates. table 17.9 lists an example of bit rates and settings. table 17.9 example of bit rates and settings bit rate (bps) count source of uibrg peripheral function clock: 16 mhz peripheral function clock: 24 mhz set value of uibrg: n bit rate (bps) set value of uibrg: n bit rate (bps) 1200 f8sio 103 (67h) 1202 155 (9bh) 1202 2400 f8sio 51 (33h) 2404 77 (4dh) 2404 4800 f8sio 25 (19h) 4808 38 (26h) 4808 9600 f1sio 103 (67h) 9615 155 (9bh) 9615 14400 f1sio 68 (44h) 14493 103 (67h) 14423 19200 f1sio 51 (33h) 19231 77 (4dh) 19231 28800 f1sio 34 (22h) 28571 51 (33h) 28846 31250 f1sio 31 (1fh) 31250 47 (2fh) 31250 38400 f1sio 25 (19h) 38462 38 (26h) 38462 51200 f1sio 19 (13h) 50000 28 (1ch) 51724 d0 d1 d7 start bit reception triggered when transfer clock is generated by falling edge of start bit sampled ?l? receive data taken in uibrg count source re bit in uic1 register rxdi transfer clock ri bit in uic1 register rtsi stop bit ?1? ?0? ?0? ?1? ?h? ?l? the above timing diagram applies to the case where the register bits are set as follows: the prye bit in the uimr register = 0 (parity disabled) the stps bit in the uimr register = 0 (1 stop bit) the crd bit in the uic0 register = 0 (ctsi / rtsi enabled) and the crs bit = 1 (rtsi selected) i = 0 to 2, 5 to 7 ir bit in siric register ?0? ?1? set to 0 by an interrupt request acknowledgement or by program transferred from uarti receive register to uirb register example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) rej09b0392-0064 rev.0.64 oct 12, 2007 page 199 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.2.2 counter measure fo r communication error if a communication error occurs while transmitting or receiving in uart mo de, follow the procedures below. ? resetting the uirb register (i = 0 to 2, 5 to 7) (1) set the re bit in the uic1 register to 0 (reception disabled) (2) set the re bit in the uic1 register to 1 (reception enabled) ? resetting the uitb register (1) set bits smd2 to smd0 in the uimr register to 000b (serial interface disabled) (2) reset bits smd2 to smd0 in the uimr register to 001b, 101b, and 110b. (3) 1 is written to the re bit in the uic1 register (transmission enabled), regardless of the te bit in the uic1 register 17.1.2.3 lsb first / msb first select function as shown in figure 17.20, use the uform bit in the uic0 register to select the transfer format. this function is valid when transfer data is 8 bits long. figure 17.20 transfer format (1) when the uform bit in the uic0 register = 0 (lsb first) d1 d2 d3 d4 d5 d6 sp d0 d1 d2 d3 d4 d5 d6 sp d0 txdi rxdi clki (2) when the uform bit in the uic0 register = 1 (msb first) d6 d5 d4 d3 d2 d1 d0 d7 txdi rxdi clki the above applies to the case where the ckpol bit in the uic0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the uilch bit in the uic1 register = 0 (no reverse), the stps bit in the uimr re gister = 0 (1 stop bit), and the prye bit in the uimr re gister = 1 (parity enabled). st st d7 p d7 p sp sp st st p p d6 d5 d4 d3 d2 d1 d0 d7 st : start bit p : parity bit sp : stop bit i = 0 to 2, 5 to 7 rej09b0392-0064 rev.0.64 oct 12, 2007 page 200 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.2.4 serial data l ogic switching function the data written to the uitb register has its logi c reversed before being transmitted. similarly, the received data has its logic reversed when read from the uirb register. figure 17.21 shows serial data logic switching. figure 17.21 serial data logic switching 17.1.2.5 txd and rxd i/o polarity reverse function this function reverses the polarities of the txdi pi n output and rxdi pin input. the logic levels of all input / output data (including bits for start, stop, and parity) are reversed. figure 17.22 shows the txd and rxd i/o polarity reverse. figure 17.22 txd and rxd i/o polarity reverse d0 d1 d2 d3 d4 d5 d6 d7 p sp st sp st d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txdi (no reverse) txdi (reverse) ?h? ?l? ?h? ?l? ?h? ?l? (1) when the uilch bit in the uic1 register = 0 (no reverse) transfer clock ?h? ?l? (2) when the uilch bit in the uic1 register = 1 (reverse) st : start bit p : parity bit sp : stop bit i = 0 to 2, 5 to 7 the above applies to the case where the ckpol bit in the uic0 register = 0 (transmit data output at the falling edge of the transfer clock), the uform bit in the uic0 register = 0 (lsb first), the stps bit in the uimr register = 0 (1 stop bit), and the prye bit in the uimr register = 1 (parity enabled). st: start bit p : parity bit sp: stop bit i = 0 to 2, 5 to 7 d0 d1 d2 d3 d4 d5 d6 d7 p sp st sp st d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txdi (no reverse) txdi (reverse) ?h? ?l? ?h? ?l? ?h? ?l? (1) when the iopol bit in the uimr register = 0 (no reverse) the above applies to the case where the uform bit in the uic0 register = 0 (lsb first), the stps bit in the uimr register = 0 (1 stop bit), and the prye bit in the uimr register = 1 (parity enabled). transfer clock ?h? ?l? (2) when the iopol bit in the uimr register = 1 (reverse) d0 d1 d2 d3 d4 d5 d6 d7 p sp st rxdi (no reverse) ?h? ?l? sp st d3 d4 d5 d6 d7 p d0 d1 d2 rxdi (reverse) ?h? ?l? rej09b0392-0064 rev.0.64 oct 12, 2007 page 201 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.2.6 cts / rts function the cts function is used to start transmit operation when ?l? is applied to the ctsi / rtsi (i = 0 to 2, 5 to 7) pin. transmit operation begins when the ctsi / rtsi pin is held ?l?. if the ?l? signal is switched to ?h? during a transmit operation, th e operation stops after the ongoing transmit / receive operation is completed. when the rts function is used, the ctsi / rtsi pin outputs ?l? when the microcomputer is ready to receive. the output level becomes ?h ? on the first falling edge of the clki pin. ? crd bit in the uic0 register = 1 (disable cts / rts function) ctsi / rtsi pin is programmable i/o function ? the crd bit = 0, the crs bit = 0 ( cts function is selected) ctsi / rtsi pin is cts function ? the crd bit = 0, the crs bit = 1 ( rts function is selected) ctsi / rtsi pin is rts function 17.1.2.7 cts / rts separate function (uart0) this function separates cts0 / rts0 , outputs rts0 from the p6_0 pin, and inputs cts0 from the p6_4 pin. to use this function, set the register bits as shown below. ? the crd bit in the u0c0 register = 0 (enable cts / rts of uart0) ? the crs bit in the u0c0 register = 1 (output rts of uart0) ? the crd bit in the u1c0 register = 0 (enable cts / rts of uart1) ? the crs bit in the u1c0 register = 0 (input cts of uart1) ? the rcsp bit in the ucon register = 1 (inputs cts0 from the p6_4 pin) ? the clkmd1 bit in the ucon register = 0 (clks1 not used) note that when using the cts / rts separate function, cts / rts of uart1 function cannot be used. figure 17.23 cts / rts separate function microcomputer txd0 (p6_3) rxd0 (p6_2) in out cts rts cts0 (p6_4) rts0 (p6_0) ic rej09b0392-0064 rev.0.64 oct 12, 2007 page 202 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.3 special mode 1 (i 2 c mode) i 2 c mode is provided for use as a simplified i 2 c interface compatible mode. table 17.10 lists the speci- fications of i 2 c mode. tables 17.11 and 17.12 list the registers used in i 2 c mode and the register val- ues set. table 17.13 lists the i 2 c mode functions. figure 17.24 shows the block diagram for i 2 c mode. figure 17.25 shows transfer to uirb register and interrupt timing. as shown in table 17.13, the mi crocomputer is placed in i 2 c mode by setting bits smd2 to smd0 to 010b and the iicm bit to 1. because sdai transmit output has a delay circuit attached, sdai output does not change state until scli goes low and remains stably low. i = 0 to 2, 5 to 7 notes: 1. when an external clock is selected, the conditions must be met while the external clock is in high state. 2. if an overrun error occurs , the received data of th e uirb register will be in determinate. the ir bit in the siric register does not change. table 17.10 i 2 c mode specifications item specification transfer data format transfer data length: 8 bits transfer clock ? during master ckdir bit in the uimr register = 0 (internal clock): fj / (2(n+1)) fj = f1sio, f2sio, f8sio, f32sio n = setting value of the uibrg register 00h to ffh ? during slave ckdir bit = 1 (external clock): input from the scli pin transmission start condi- tion before transmission starts, sa tisfy the following requirements (1) ? the te bit in the uic1 register = 1 (transmission enabled) ? the ti bit in the uic1 register = 0 (data present in uitb register) reception start condition before reception starts, sati sfy the following requirements (1) ? the re bit in the uic1 register = 1 (reception enabled) ? the te bit in the uic1 register = 1 (transmission enabled) ? the ti bit in the uic1 register = 0 (data present in the uitb register) interrupt request generation timing when start or stop condition is de tected, acknowledge undetected, or acknowledge detected error detection overrun error (2) this error occurs if the serial interface started receiving the next data before reading the uirb register and received the 8th bit of the next data select function ? arbitration lost timing at which the abt bit in the ui rb register is updated can be selected ? sdai digital delay no digital delay or a delay of 2 to 8 uibrg count source clock cycles selectable ? clock phase setting with or without cl ock delay selectable rej09b0392-0064 rev.0.64 oct 12, 2007 page 203 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.24 i 2 c mode block diagram delay circuit transmission register sdai scli reception register clk control internal clock uarti external clock arbitration start condition detection stop condition detection port register (1) falling edge detection d t q d t q d t q nack ack uarti uarti uarti r uarti transmit, nack interrupt request uarti receive, ack interrupt request, dma1, dma3 request 9th bit iicm = 1 and iicm2 = 0 s r q bus busy start / stop condition detection interrupt request als r s swc 9th bit falling edge iicm = 1 and iicm2 = 0 iicm2 = 1 iicm2 = 1 swc2 sdhi dma0 to dma3 request i = 0 to 2, 5 to 7 this diagram applies to the case where bits smd2 to smd0 in th e uimr register = 010b and the iicm bit in the uismr register = 1 . iicm : bit in the uismr register iicm2, swc, als, swc2, sdhi : bits in the uismr2 register stspsel, ackd, ackc : bits in the uismr4 register iicm = 0 iicm = 1 i/o port dma0, dma2 request stspsel=0 stspsel = 1 stspsel = 1 stspsel = 0 sda (stsp) scl (stsp) ackc = 1 ackc = 0 ackd bit if the iicm bit = 1, the pin can be read even when the port direction bit corresponding to the scli pin = 1 (output mode). q start and stop condition generation block noise filter noise filter rej09b0392-0064 rev.0.64 oct 12, 2007 page 204 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface i = 0 to 2, 5 to 7 notes: 1. set the bit 4 and bit 5 in registers u0c1 and u1c1 to 0. bits u0irs, u1irs, u0rrm, and u1rrm are in the ucon register. 2. the txd2 pin is n channel open-drain output. no nch bit in the u2c0 register is assigned. when write, set to 0. 3. set the bits not listed above to 0 when writing to the registers in i 2 c mode. 4. when using uart1 in i 2 c mode and enabling the cts / rts separate function of uart0, set the crd bit in the u1c0 register to 0 ( cts / rts enabled) and the crs bit to 0 ( cts input). table 17.11 registers to be used and settings in i 2 c mode (1) register bit function master slave uitb 0 to 7 set transmission data set transmission data uirb (3) 0 to 7 reception data can be read reception data can be read 8 ack or nack is set in this bit ack or nack is set in this bit abt arbitration lost detection flag invalid oer overrun error flag overrun error flag uibrg 0 to 7 set a bit rate invalid uimr (3) smd2 to smd0 set to 010b set to 010b ckdir set to 0 set to 1 iopol set to 0 set to 0 uic0 clk1, clk0 select the count source for the uibrg reg- ister invalid crs invalid because crd = 1 invalid because crd = 1 txept transmit register empty flag transmit register empty flag crd (4) set to 1 set to 1 nch set to 1 (2) set to 1 (2) ckpol set to 0 set to 0 uform set to 1 set to 1 uic1 te set this bit to 1 to enable transmission set this bit to 1 to enable transmission ti transmit buffer empty flag transmit buffer empty flag re set this bit to 1 to enable reception set this bit to 1 to enable reception ri reception complete flag reception complete flag uiirs (1) invalid invalid uirrm (1) , uilch, uiere set to 0 set to 0 uismr iicm set to 1 set to 1 abc select the timing at which arbitration lost is detected invalid bbs bus busy flag bus busy flag 3 to 7 set to 0 set to 0 uismr2 iicm2 see table 17.13 i 2 c mode functions see table 17.13 i 2 c mode functions csc set this bit to 1 to enable clock synchroniza- tion set to 0 swc set this bit to 1 to have scli output fixed to ?l? at the falling edge of the 9th bit of clock set this bit to 1 to have scli output fixed to ?l? at the falling edge of the 9th bit of clock als set this bit to 1 to have sdai output stopped when arbitration lost is detected set to 0 stac set to 0 set this bit to 1 to initialize uarti at start condition detection swc2 set this bit to 1 to have scli output forcibly pulled low set this bit to 1 to have scli output forcibly pulled low sdhi set this bit to 1 to disable sdai output set this bit to 1 to disable sdai output 7 set to 0 set to 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 205 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface i = 0 to 2, 5 to 7 table 17.12 registers to be used and settings in i 2 c mode (2) register bit function master slave uismr3 0, 2, 4, and nodc set to 0 set to 0 ckph see table 17.13 ?i 2 c mode func- tions? see table 17.13 ?i 2 c mode func- tions? dl2 to dl0 set the amount of sdai digital delay set the amount of sdai digital delay uismr4 stareq set this bit to 1 to generate start condi- tion set to 0 rstareq set this bit to 1 to generate restart con- dition set to 0 stpreq set this bit to 1 to generate stop condi- tion set to 0 stspsel set this bit to 1 to output each condition set to 0 ackd select ack or nack select ack or nack ackc set this bit to 1 to output ack data set this bit to 1 to output ack data sclhi set this bit to 1 to have scli output stopped when stop condition is detected set to 0 swc9 set to 0 set this bit to 1 to set the scli to ?l? hold at the falling edge of the 9th bit of clock ifsr2a ifsr26, isfr27 set to 1 set to 1 ucon u0irs, u1irs invalid invalid 2 to 7 set to 0 set to 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 206 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface i = 0 to 2, 5 to 7 notes: 1. if the source or factor of any interrupt is changed, the ir bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 (interrupt requested). (refer to 24.7 ?interrupt? ) if one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. therefore, always be sure to clear the ir bit to 0 (interrupt not requested) after changing those bits. bits smd2 to smd0 in the uimr register, the iicm bit in the uismr register, the iicm2 bit in the uismr register, and the ckph bit in the uismr3 register 2. set the initial value of sdai output while bits smd2 to smd0 in the uimr register = 000b (serial interface disabled). 3. second data transfer to the uirb register (rising edge of scli 9th bit) 4. first data transfer to the uirb register (falling edge of scli 9th bit) 5. see figure 17.27 ?stspsel bit functions? . 6. see figure 17.25 ?transfer to uirb register and interrupt timing? . 7. when using uart0, be sure to set the ifsr26 bit in the ifsr2a register to 1 (factor of interrupt: uart0 bus collision). when using uart1, be sure to set the ifsr27 bit in t he ifsr2a register to 1 (factor of interrupt: uart1 bus collision). table 17.13 i 2 c mode functions function clock synchronous serial i/o mode (smd2 to smd0 = 001b, iicm = 0 ) i 2 c mode (smd2 to smd0 = 010b, iicm = 1) iicm2 = 0 (nack/ack interrupt) iicm2 = 1 (uart transmit / receive interrupt) ckph = 0 (no clock delay) ckph = 1 (clock delay) ckph = 0 (no clock delay) ckph = 1 (clock delay) factor of interrupt number 5, 6, 7, 10, 27, and 28 (1, 5, 7) ) - start condition detection or stop condition detection (see table 17.14 ?stspsel bit functions? ) factor of interrupt number 15, 17, 19, 21, 23, and 24 (1, 6) uarti transmission transmission started or completed (selected by uiirs) no acknowledgment detection (nack) rising edge of scli 9th bit uarti transmission rising edge of scli 9th bit uarti transmission falling edge of scli next to the 9th bit factor of interrupt number 16, 18, 20, 22, 25, and 26 (1, 6) uarti reception when 8th bit received ckpol = 0 (rising edge) ckpol = 1 (falling edge) acknowledgment detection (ack) rising edge of scli 9th bit uarti reception falling edge of scli 9th bit timing for transferring data from the uart reception shift register to the uirb register ckpol = 0 (rising edge) ckpol = 1 (falling edge) rising edge of scli 9th bit falling edge of scli 9th bit falling and rising edges of scli 9th bit uarti transmission out- put delay not delayed delayed functions of txdi / sdai tx di output sdai input / output functions of rxdi / scli rxdi input scli input / output functions of clki clki input or output port selected ? (cannot be used in i 2 c mode) noise filter width 15ns 200ns read rxdi and scli pin levels possible when the corre- sponding port direction bit = 0 always possible no matter how the corresponding port direction bit is set initial value of txdi and sdai outputs ckpol = 0 (?h?) ckpol = 1 (?l?) the value set in the port register before setting i 2 c mode (2) initial and end values of scli - ?h? ?l? ?h? ?l? dma1 factor (6) uarti reception acknowledgment detection (ack) uarti reception falling edge of scli 9th bit store received data 1st to 8th bits of the received data are stored into bits 0 to 7 in the uirb register 1st to 8th bits of the received data are stored into bits 7 to 0 in the uirb register 1st to 7th bits of the received data are stored into bits 6 to 0 in the uirb register. 8th bit is stored into bit 8 in the uirb register 1st to 8th bits are stored into bits 7 to 0 in the uirb register (3) read received data the uirb register stat us is read bits 6 to 0 in the uirb register are read as bits 7 to 1. bit 8 in the uirb register is read as bit 0 (4) rej09b0392-0064 rev.0.64 oct 12, 2007 page 207 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.25 transfer to uirb register and interrupt timing (1) iicm2 = 0 (ack and nack interrupts), ckph = 0 (no clock delay) d6 d5 d4 d3 d2 d1 d8 (ack, nack) d7 sdai scli d0 ack interrupt (dma1, dma3 request), nack interrupt transfer to uirb register b15 ... b9 b8 b7 b0 uirb register d8 d7 d6 d5 d4 d3 d2 d1 d0 (2) iicm2 = 0, ckph = 1 (clock delay) d6 d5 d4 d3 d2 d1 d7 sdai scli d0 ack interrupt (dma1, dma3 request), nack interrupt transfer to uirb register b15 ... b9 b8 b7 b0 d8 d7 d6 d5 d4 d3 d2 d1 d0 uirb register d8 (ack, nack) (3) iicm2 = 1 (uart transmit / receive interrupt), ckph = 0 d6 d5 d4 d3 d2 d1 d7 sdai scli d0 receive interrupt (dma1, dma3 request) transmit interrupt transfer to uirb register b15 ... b9 b8 b7 b0 d0 d7 d6 d5 d4 d3 d2 d1 uirb register d8 (ack, nack) (4) iicm2 = 1, ckph = 1 d6 d5 d4 d3 d2 d1 d7 sdai scli d0 transmit interrupt transfer to uirb register i = 0 to 2, 5 to 7 this diagram applies to the case where the following condition is met. the ckdir bit in the uimr register = 0 (slave selected) receive interrupt (dma1, dma3 request) b15 ... b9 b8 b7 b0 d0 d7 d6 d5 d4 d3 d2 d1 uirb register transfer to uirb register b15 ... b9 b8 b7 b0 d8 d7 d6 d5 d4 d3 d2 d1 d0 uirb register d8 (ack, nack) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit rej09b0392-0064 rev.0.64 oct 12, 2007 page 208 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.3.1 detection of st art and stop condition whether a start or a stop condition has been detected is determined. a start condition detect interrupt request is generated when the sdai pin changes state from high to low while the scli pin is in the high state. a stop condition detect interrupt request is generated when the sdai pin changes state from low to high while the scli pin is in the high state. because the start and stop condition detect interrupt s share the interrupt control register and vector, check the bbs bit in the uismr r egister to determine which interrupt source is requesting the inter- rupt. figure 17.26 detection of start and stop condition 17.1.3.2 output of st art and stop condition a start condition is generated by setting the stareq bi t in the uismr4 register (i = 0 to 2, 5 to 7) to 1 (start). a restart condition is generated by setting the rstareq bit in the uismr4 register to 1 (start). a stop condition is generated by setting the stpr eq bit in the uismr4 register to 1 (start). the output procedure is described below. (1) set the stareq bit, rstareq bit or stpreq bit to 1 (start). (2) set the stspsel bit in the uismr4 register to 1 (output). the function of the stspsel bit is shown in tables 17.14 and 17.27. duration for setting up duration for holding scli sdai (start condition) sda i (stop condition) i = 0 to 2, 5 to 7 when the pclk1 bit in the pclkr register = 1, this is the cycle number of f1sio, and the pclk1 bit = 0, the cycle number of f2sio. 3 to 6 cycles < duration for setting-up (1) 3 to 6 cycles < duration for holding (1) rej09b0392-0064 rev.0.64 oct 12, 2007 page 209 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.27 stspsel bit functions 17.1.3.3 arbitration unmatching of the transmit data and sdai pin i nput data is checked synchronously with the rising edge of scli. use the abc bit in the uismr register to select the timing at which the abt bit in the uirb register is updated. if the abc bit = 0 (update per bit), the abt bit is set to 1 at the same time unmatching is detected during check, and is cleared to 0 when not detected. in cases when the abc bit is set to 1, if unmatching is ever detected, the abt bit is set to 1 (unmatching detected) at the fall- ing edge of the clock pulse of 9th bit. if the abt bit needs to be updated per byte, clear the abt bit to 0 (undetected) after detecting acknowledge in the first byte, before tran sferring the next byte. setting the als bit in the uismr2 register to 1 (s da output stop enabled) fa ctors arbitration-lost to occur, in which case the sdai pin is placed in the high-impedance state at the same time the abt bit is set to 1 (unmatching detected). table 17.14 stspsel bit functions function stspsel = 0 stspsel = 1 output of pins scli and sdai output of transfer clock and data output of start / stop condition is accomplished by a program using ports (not automatically generated in hardware) output of a start / stop condition according to bits stareq, rstareq, and stpreq start / stop condition interrupt request genera- tion timing detect start / stop condition complete generating start / stop con- dition sdai start condition detection interrupt stop condition detection interrupt (1) when slave ckdir = 1 (external clock) scli sdai start condition detection interrupt stop condition detection interrupt (2) when master ckdir = 0 (internal clock), ckph = 1 (clock delayed) scli set stareq = 1 (start) set stpreq=1 (start) stspsel bit 0 stspsel bit set to 1 in a program set to 0 in a program set to 1 in a program set to 0 in a program 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit i = 0 to 2, 5 to 7 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit rej09b0392-0064 rev.0.64 oct 12, 2007 page 210 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.3.4 transfer clock the transfer clock is used to transmit and receive data as is shown in figure 17.25 transfer to uirb register and interrupt timing. the csc bit in the uismr2 register is used to synchronize the internally generated clock (internal scli) and an external clock supplied to the scli pin. in cases when the csc bit is set to 1 (clock synchronization enabled), if a falling edge on the scli pin is detected while the internal scli is high, the internal scli goes low, at which time the value of the uibrg register is reloaded with and starts counting in the low-level interval. if the internal scli changes state from low to high while the scli pin is low, counting stops, and when the scli pin goes high, counting restarts. in this way, the uarti transfer clock is equivalent to and of the internal scli and the clock signal applied to the scli pin. the transfer clock works be tween a half cycle before the falling edge of the internal scli 1st bit and the rising edge of the 9th bit. to use this function, select an internal clock for the transfer clock. the swc bit in the uismr2 register determines whether the scli pin is fixed to be or freed from low- level output at the falling edge of the 9th clock pulse. if the sclhi bit in the uismr4 register is set to 1 (enabled), scli output is turned off (placed in the high-impedance state) when a stop condition is detected. setting the swc2 bit in the uismr2 register = 1 (0 output) makes it possible to forc ibly output a low- level signal from the scli pin even while sending or receiving data. clearing the swc2 bit to 0 (transfer clock) allows the transfer clock to be output from or supplie d to the scli pin, instead of out- putting a low-level signal. if the swc9 bit in the uismr4 register is set to 1 (scl hold low enabled) when the ckph bit in the uismr3 register = 1, the scli pi n is fixed to low-level output at the falling edge of the clock pulse next to the 9th. setting the swc9 bit = 0 (scl hold low disabled) frees the scli pin from low-level output. 17.1.3.5 sda output the data written to bits 7 to 0 (d7 to d0) in the uitb register is output in descending order from d7. the 9th bit (d8) is ack or nack. set the initial value of sdai tr ansmit output when iicm = 1 (i 2 c mode) and bits smd2 to smd0 in the uimr register = 000b (serial interface disabled). bits dl2 to dl0 in the uismr3 register allow to add no delays or a delay of 2 to 8 uibrg count source clock cycles to sdai output. setting the sdhi bit in the uismr2 register = 1 (sda output disabled) forcibly places the sdai pin in the high-impedance state. do not write to the sdhi bit at the rising edge of the uarti transfer clock. this is because the abt bit may inad vertently be set to 1 (detected). 17.1.3.6 sda input when the iicm2 bit = 0, the 1st to 8th bits (d7 to d0 ) of received data are stored in bits 7 to 0 in the uirb register. the 9th bi t (d8) is ack or nack. when the iicm2 bit = 1, the 1st to 7th bits (d7 to d1 ) of received data are stored in bits 6 to 0 in the uirb register and the 8th bit (d0) is stored in bit 8 in the uirb register. even when the iicm2 bit = 1, providing the ckph bit = 1, the same data as when the iicm2 bit = 0 can be read. to read the data, read the uirb register after the rising edge of 9th bit of the corresponding clock pulse. rej09b0392-0064 rev.0.64 oct 12, 2007 page 211 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.3.7 ack and nack if the stspsel bit in the uismr4 re gister is set to 0 (start and st op conditions no t generated) and the ackc bit in the uismr4 register is set to 1 (a ck data output), the value of the ackd bit in the uismr4 register is output from the sdai pin. if the iicm2 bit = 0, the nack interrupt request is generated if the sdai pin remains high at the rising edge of the 9th bit of transmit clock pulse. the ac k interrupt request is generat ed if the sdai pin is low at the rising edge of the 9th bit of transmit clock pulse. if acki is selected to generate a dma1 or dma3 request source, a dma transfer can be activated by detection of an acknowledge. 17.1.3.8 initialization of transmission / reception if a start condition is detected while the stac bit = 1 (uarti initialization en abled), the serial inter- face operates as described below. ? the transmit shift register is in itialized, and the content of the uitb register is transferred to the transmit shift register. in this way, the serial in terface starts sending data synchronously with the next clock pulse applied. however, the uarti outp ut value does not change state and remains the same as when a start condition was detected until the first bit of data is output synchronously with the input clock. ? the receive shift register is init ialized, and the serial interface starts receiving data synchronously with the next clock pulse applied. ? the swc bit is set to 1 (scl wait output enable d). consequently, the scli pin is pulled low at the falling edge of the 9th clock pulse. note that when uarti transmissi on / reception is started using th is function, the ti bit does not change state. select the external clock as the tr ansfer clock to start uarti transmission / reception with this setting. rej09b0392-0064 rev.0.64 oct 12, 2007 page 212 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.4 special mode 2 in special mode 2, serial communication between one or multiple masters and mu ltiple slaves is avail- able. transfer clock polarity and phase are selectable. table 17.15 lists the special mode 2 specifica- tions. table 17.16 lists the registers to be used and settings in special mode 2. figure 17.28 shows special mode 2 communication control example (uart2). i = 0 to 2, 5 to 7 notes: 1. when an external clock is selected, the conditions must be met while if the ckpol bit in the uic0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in high state; if the ckpol bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in low state. 2. if an overrun error occurs, the received data of the uirb register will be indeterminate. the ir bit in the siric register does not change. figure 17.28 special mode 2 comm unication control example (uart2) table 17.15 special mode 2 specifications item specification transfer data format transfer data length: 8 bits transfer clock ? master mode the ckdir bit in the uimr register = 0 (internal clock): fj / (2(n + 1)) fj = f1sio, f2sio, f8sio, f32sio n: setting value of uibrg register 00h to ffh ? slave mode ? the ckdir bit = 1 (external clock selected): input from the clki pin transmit / receive control controlled by input / output ports transmission start condition before transmission starts, satisfy the following requirements (1) ? the te bit in the uic1 register = 1 (transmission enabled) ? the ti bit in the uic1 register = 0 (data present in uitb register) reception start condition before reception starts, satisfy the following requirements (1) ? the re bit in the uic1 register = 1 (reception enabled) ? the te bit = 1 (transmission enabled) ? the ti bit = 0 (data present in the uitb register) interrupt request generation timing while transmitting, one of the following conditions can be selected ? the uiirs bit in the uic1 register= 0 (transmit buffer empty): when transferring data from the uitb register to the uarti transmit register (at start of transmission) ? the uiirs bit =1 (transfer completed): wh en the serial i nterface completed sending data from the uarti transmit register while receiving ? when transferring data from the uarti receive register to the uirb register (at completion of reception) error detection overrun error (2) this error occurs if the serial interface starts receiving the next data before reading the uirb register and receives the 7th bit of the next data select function clock phase setting selectable from four combinations of transfer clock polarities and phases p1_3 p1_2 p7_0(txd2) p7_2(clk2) p7_1(rxd2) p9_3 p7_0(txd2) p7_2(clk2) p7_1(rxd2) p9_3 p7_0(txd2) p7_2(clk2) p7_1(rxd2) microcomputer (master) microcomputer (slave) microcomputer (slave) rej09b0392-0064 rev.0.64 oct 12, 2007 page 213 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface i = 0 to 2, 5 to 7 notes: 1. set bits 4 and 5 in registers u0c0 and u1c1 to 0. bits u0irs, u1irs, u0rrm, and u1rrm are in the ucon register. 2. the txd2 pin is n channel open-drain output. no nch bit in the u2c0 register is assigned. when write, set to 0. 3. set the bits not listed above to 0 when writing to the registers in special mode 2. table 17.16 registers to be used and settings in special mode 2 register bit function uitb (3) 0 to 7 set transmission data uirb (3) 0 to 7 reception data can be read oer overrun error flag uibrg 0 to 7 set a bit rate uimr (3) smd2 to smd0 set to 001b ckdir set to 0 in master mode or 1 in slave mode iopol set to 0 uic0 clk0, clk1 select the count source for the uibrg register crs invalid because crd = 1 txept transmit register empty flag crd set to 1 nch select txdi pin output format (2) ckpol clock phases can be set in combination with the ckph bit in the uismr3 register uform set to 0 uic1 te set to 1 to enable transmission / reception ti transmit buffer empty flag re set to 1 to enable reception ri reception complete flag uiirs (1) select uart2 transmit interrupt source uirrm (1) ,uilch, uiere set to 0 uismr 0 to 7 set to 0 uismr2 0 to 7 set to 0 uismr3 ckph clock phases can be set in combination with the ckpol bit in the uic0 register nodc set to 0 0, 2, 4 to 7 set to 0 uismr4 0 to 7 set to 0 ucon u0irs, u1irs select uart0 and uart1 transmit interrupt source u0rrm, u1rrm set to 0 clkmd0 invalid because clkmd1 = 0 clkmd1, rcsp, 7 set to 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 214 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.4.1 clock phase setting function one of four combinations of transfer clock phases and polarities can be selected using the ckph bit in the uismr3 register and the ckpol bit in the uic0 register. make sure the transfer clock polarity and phase ar e the same for the master and salves to be com- municated. figure 17.29 shows the transmission and reception timing in master mode (internal clock). figure 17.30 shows the transmission and receptio n timing (ckph = 0) in slave mode (external clock) while figure 17.31 show s the transmission and reception timing (ckph = 1) in slave mode (external clock). figure 17.29 transmission and reception timing in master mode (internal clock) data output timing data input timing clock output (ckpol = 0, ckph = 0) ?h? ?l? clock output (ckpol = 1, ckph = 0) clock output (ckpol = 0, ckph = 1) clock output (ckpol = 1, ckph = 1) ?h? ?l? ?h? ?l? ?h? ?l? ?h? ?l? d0 d1 d2 d3 d4 d6 d7 d5 rej09b0392-0064 rev.0.64 oct 12, 2007 page 215 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.30 transmission and reception timing (ckph = 0) in slave mode (external clock) figure 17.31 transmission and reception timing (ckph = 1) in slave mode (external clock) slave control input clock input (ckpol = 0, ckph = 0) clock input (ckpol = 1, ckph = 0) data output timing (1) data input timing ?h? ?l? ?h? ?l? ?h? ?l? ?h? ?l? d0 d1 d2 d3 d4 d6 d7 d5 unde- fined note: 1. uart2 output is an n-channel open drain and must be pulled-up externally. slave control input clock input (ckpol=0, ckph=1) clock input (ckpol=1, ckph=1) data output timing (1) data input timing d0 d1 d2 d3 d6 d7 d4 d5 ?h? ?l? ?h? ?l? ?h? ?l? ?h? ?l? note: 1. uart2 output is an n-channel open drain and must be pulled-up externally. rej09b0392-0064 rev.0.64 oct 12, 2007 page 216 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.5 special m ode 3 (ie mode) in this mode, one bit of iebus is approximated with one byte of uart mode waveform. table 17.17 lists the registers to be used and setti ngs in ie mode. figure 17.32 shows the bus colli- sion detect function-related bits. if the txdi pin (i = 0 to 2, 5 to 7) output level and rxdi pin input level do not match, a uarti bus colli- sion detect interrupt request is generated. use bits ifsr26 and ifsr27 in the ifsr2a register to enable the uart0 / uart1 bus collision detect function. i = 0 to 2, 5 to 7 notes: 1. set bits 4 and 5 in registers u0c0 and u1c1 to 0. bits u0irs, u1irs, u0rrm, and u1rrm are in the ucon register. 2. the txd2 pin is n channel open-drain output. no nch bit in the u2c0 register is assigned. when write, set to 0. 3. set the bits not listed above to 0 when writing to the registers in ie mode. table 17.17 registers to be used and settings in ie mode register bit function uitb 0 to 8 set transmission data uirb (3) 0 to 8 reception data can be read oer, fer, per, sum error flag uibrg 0 to 7 set a bit rate uimr smd2 to smd0 set to 110b ckdir select the internal clock or external clock stps set to 0 pry invalid because prye = 0 prye set to 0 iopol select the txd and rxd input / output polarity uic0 clk1, clk0 select the count source for the uibrg register crs invalid because crd = 1 txept transmit register empty flag crd set to 1 nch select txdi pin output format (2) ckpol set to 0 uform set to 0 uic1 te set to 1 to enable transmission ti transmit buffer empty flag re set to 1 to enable reception ri reception complete flag uiirs (1) select the source of uarti transmit interrupt uirrm (1) , uilch, uiere set to 0 uismr 0 to 3, 7 set to 0 abscs select the sampling timing at which to detect a bus collision acse set this bit to 1 to use the auto clear function of transmit enable bit sss select the transmit start condition uismr2 0 to 7 set to 0 uismr3 0 to 7 set to 0 uismr4 0 to 7 set to 0 ifsr2a ifsr26, ifsr27 set to 1 ucon u0irs, u1irs select the source of uart0 / uart1 transmit interrupt u0rrm, u1rrm set to 0 clkmd0 invalid because clkmd1 = 0 clkmd1, rcsp, 7 set to 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 217 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.32 bus collision detect function-related bits (1) the abscs bit in the uismr register (bus collision detect sampling clock select) if abscs = 0, bus collision is determined at the rising edge of the transfer clock transfer clock timer aj (2) the acse bit in the uismr register (auto clear of transmit enable bit) ir bit in uibcnic and bcnic register te bit in uic1 register (3) the sss bit in the uismr register (transmit start condition select) txdi transmit enable conditions are met clki txdi rxdi notes : 1. the falling edge of rxdi when iopol = 0; the rising edge of rxdi when iopol = 1. 2. the transmit condition must be met before the falling edge of rxd (1) . if sss bit = 0, the serial interface starts sending data one transfer clock cycle after the transmission enable condition is met. txdi rxdi st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp trigger signal is applied to the tajin pin if abscs = 1, bus collision is determined when timer aj (one-shot timer mode) underflows. timer aj: timer a3 in uart0; timer a4 in uart1; timer a0 in uart2 timer a0 in uart5; timer a3 in uart6; timer a4 in uart7 transfer clock txdi rxdi st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp transfer clock st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp if sss bit = 1, the serial interface starts sending data at the rising edge of rxdi (1) (2) (i = 0 to 2, 5 to 7) the above diagram applies to the case where iopol = 1 (reversed). if acse bit = 1 (automatically clear when bus collision occurs), the te bit is cleared to 0 (transmission disabled) when the ir bit in the uibcnic register = 1 (unmatching detected). i = 0 to 2, 5 to 7 rej09b0392-0064 rev.0.64 oct 12, 2007 page 218 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.6 special mode 4 (sim mode) (uart2) sim interface devices can communicate in uart mode. both direct and inverse formats are avail- able. the txd2 pin outputs a low-level signal when a parity error is detected. table 17.18 lists the sim mode specifications. tabl e 17.19 lists the registers to be used and set- tings in sim mode. notes: 1. if an overrun error occurs, the received data of th e u2rb register will be i ndeterminate. the ir bit in the s2ric register does not change. 2. a transmit interrupt request is generated by setti ng the u2irs bit to 1 (transmission completed) and the u2ere bit to 1 (error signal output) in the u2c1 register after reset is canceled. therefore, when using sim mode, set the ir bit to 0 (interru pt not requested) after setting the bits. 3. the timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the uart2 receive register to the u2rb register. table 17.18 sim mode specifications item specification transfer data format ? direct format ? inverse format transfer clock ? the ckdir bit in the u2mr regi ster = 0 (internal clock): fi / (16(n + 1)) fi = f1sio, f2sio, f8sio, f32sio n = setting value of the u2brg register 00h to ffh ? the ckdir bit = 1 (external clock): fext / (16(n + 1)) fext = input from the clk2 pin n = setting value of the u2brg register 00h to ffh transmission start condition before transmission starts, sa tisfy the following requirements ? the te bit in the u2c1 register = 1 (transmission enabled) ? the ti bit in the u2c1 register = 0 (data present in the u2tb register) reception start condi- tion before reception starts, sati sfy the following requirements ? the re bit in the u2c1 register = 1 (reception enabled) ? start bit detection interrupt request generation timing (2) ? while transmitting when the serial interface completed sending data from the uart2 transmit register (the u2irs bit =1) ? while receiving when transferring data from the uart2 re ceive register to the u2rb register (at completion of reception) error detection ? overrun error (1) this error occurs if the serial interface started receiving the next data before reading the u2rb register and received the bit one before the last stop bit of the next data ? framing error (3) this error occurs when the number of stop bits set is not detected ? parity error (3) during reception, if a parity error is dete cted, parity error sign al is output from the txd2 pin. during transmission, a parity error is detected by the level of input to the rxd2 pin when a transmission interrupt occurs ? error sum flag this flag is set to 1 when one of the ov errun, framing, and parity errors occurs rej09b0392-0064 rev.0.64 oct 12, 2007 page 219 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface note: 1. set the bits not listed above to 0 when writing to the registers in sim mode. table 17.19 registers to be used and settings in sim mode register bit function u2tb (1) 0 to 7 set transmission data u2rb (1) 0 to 7 reception data can be read oer,fer,per,sum error flag u2brg 0 to 7 set a bit rate u2mr smd2 to smd0 set to 101b ckdir select the internal clock or external clock stps set to 0 pry set to 1 in direct format or 0 in inverse format prye set to 1 iopol set to 0 u2c0 clk0,clk1 select the count source for the u2brg register crs invalid because crd = 1 txept transmit register empty flag crd set to 1 nch set to 0 ckpol set to 0 uform set to 0 in direct format or 1 in inverse format u2c1 te set to 1 to enable transmission ti transmit buffer empty flag re set to 1 to enable reception ri reception complete flag u2irs set to 1 u2rrm set to 0 u2lch set to 0 in direct format or 1 in inverse format u2ere set to 1 u2smr (1) 0 to 3 set to 0 u2smr2 0 to 7 set to 0 u2smr3 0 to 7 set to 0 u2smr4 0 to 7 set to 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 220 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.33 transmit and receive timing in sim mode d0 d1 d2 d3 d4 d5 d6 d7 st p start bit parity bit ?0? ?1? ?0? ?1? ?0? ?1? ?0? ?1? set to 0 by an interrupt request acknowledgement or by program d0 d1 d2 d3 d4 d5 d6 d7 st p tc transfer clock sp stop bit an ?l? signal is applied from the sim card due to a parity error an interrupt routine detects ?h? or ?l? an interrupt routine detects ?h? or ?l? d0 d1 d2 d3 d4 d5 d6 d7 st p start bit parity bit txd2 ?0? ?1? ?0? ?1? ?0? ?1? set to 0 by an interrupt request acknowledgement or by program d0 d1 d2 d3 d4 d5 d6 d7 st p tc transfer clock sp stop bit txd2 provides ?l? output due to a parity error transmit waveform from transmitting end read the u2rb register d0 d1 d2 d3 d4 d5 d6 d7 st p rxd2 pin level (3) d0 d1 d2 d3 d4 d5 d6 d7 st p sp sp d0 d1 d2 d3 d4 d5 d6 d7 st p d0 d1 d2 d3 d4 d5 d6 d7 st p sp sp txd2 parity error signal returned from receiving end rxd2 pin level (2) notes: 1. data transmission starts when brg overflows after a value is set to the u2tb register on the rising edge of the ti bit. 2. because pins txd2 and rxd2 are connected, a composit e waveform, consisting of transmit waveform from the txd2 pin and parity error signal from the receiving end, is generated. 3. because pins txd2 and rxd2 are connected, a composit e waveform, consisting of transmit waveform from the transmitting end and parity error signal from the txd2 pin, is generated. data is transfer red from the u2tb register to the uart2 transmit register (note 1) re bit in u2c1 register ri bit in u2c1 register ir bit in s2ric register te bit in u2c1 register ti bit in u2c1 register txept bit in u2c0 register ir bit in s2tic register the above timing diagram applies to the case where data is transmitted in the direct format. ? the stps bit in the u2mr register = 0 (1 stop bit) ? the pry bit in the u2mr register = 1 (even parity) ? the uform bit in the u2c0 register = 0 (lsb first) ? the u2lch bit in the u2c1 register = 0 (no reverse) ? the u2irs bit in the u2c1 register = 1 (transmit completed) tc = 16 (n + 1) / fi or 16 (n + 1) / fext fi : frequency of u2brg count source (f1sio, f2sio, f8sio, f32sio) fext : frequency of u2brg coun t source (external clock) n : value set to u2brg (1) transmit timing (2) receive timing sp the above timing diagram applies to the case where data is received in the direct format. ? the stps bit in the u2mr register = 0 (1 stop bit) ? the pry bit in the u2mr register = 1 (even parity) ? the uform bit in the u2c0 register = 0 (lsb first) ? the u2lch bit in the u2c1 register = 0 (no reverse) ? the u2irs bit in the u2c1 register = 1 (transmit completed) tc = 16 (n + 1) / fi or 16 (n + 1) / fext fi : frequency of u2brg count source (f1sio, f2sio, f8sio, f32sio) fext : frequency of u2brg count source (external clock) n : value set to u2brg sp data is written to the u2tb register rej09b0392-0064 rev.0.64 oct 12, 2007 page 221 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.34 shows an example of sim interface connection. connect txd2 and rxd2, and then place a pull-up resistance. figure 17.34 example of sim interface connection 17.1.6.1 parity error signal output the parity error signal is enabled by setting the u2ere bit in the u2c1 register to 1 (error signal out- put). the parity error signal is output when a parity error is detected while receiving data. a low-level signal is output from the txd2 pin in the timing shown in figure 17.35. if the u2rb register is read while outputting a parity error signal, the per bit is cleare d to 0 (no parity error) and at the same time the txd2 output is returned high. when transmitting, a transmi ssion complete interrupt request is generated at the falling edge of the transfer clock pulse that immediatel y follows the stop bit. therefore, whether a parity error signal has been returned can be determined by reading the port t hat shares the rxd2 pin in a transmission complete interrupt routine. figure 17.35 parity error signal output timing microcomputer sim card txd2 rxd2 st : start bit p: even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st (note 1) transfer clock rxd2 txd2 ri bit in u2c1 register this timing diagram applies to the case where the direct format is implemented. note: 1. the output of microcomputer is in the high-impedance state (pulled up externally). ?h? ?l? ?h? ?l? ?h? ?l? ?1? ?0? rej09b0392-0064 rev.0.64 oct 12, 2007 page 222 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.1.6.2 format two formats are available: direct format and inverse format. in direct format, set the prye bit in the u2mr re gister to 1 (parity enabled), the pry bit to 1(even parity), the uform bit in the u2c0 register to 0 (l sb first) and the u2lch bit in the u2c1 register to 0 (not inverted). when data are transmitted, data set in the u2tb register are transmitted with the even-numbered parity, starting from d0. when data are received, received data are stored in the u2rb register, starting from d0. the even-numbered parity determines whether a parity error occurs. in inverse format, set the prye bit to 1, the pry bit to 0 (odd parity), the uform bit to 1 (msb first), and the u2lch bit to 1 (inverted). when data are tr ansmitted, values set in the u2tb register are logically inversed and are transmitted with the odd- numbered parity, starting from d7. when data are received, received data are logically inversed to be stored in the u2rb register, starting from d7. the odd-numbered parity determines whether a parity error occurs. figure 17.36 sim interface format d0 d1 d2 d3 d4 d5 d6 d7 p transfer clock txd2 p : odd parity transfer clock txd2 d7 d6 d5 d4 d3 d2 d1 d0 p (1) direct format (2) inverse format p : even parity ?h? ?l? ?h? ?l? ?h? ?l? ?h? ?l? rej09b0392-0064 rev.0.64 oct 12, 2007 page 223 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.2 si/o3 and si/o4 si/o3 and si/o4 are exclusive cl ock-synchronous serial i/os. figure 17.37 shows the si/o3 and si/o4 block di agram, and figure 17.38 shows the registers s3c, s4c, s3brg, s4brg, s3trr, and s4trr. table 17.20 shows the si/o3 and si/o4 specifications. figure 17.37 si/o3 and si/o4 block diagram sitrr register s i/o counter i synchronous circuit data bus 8 s i / oi interrupt request smi5 lsb msb smi2 smi3 smi3 smi6 smi1 to smi0 clk i souti sini sibrg register smi6 note : i = 3, 4 n: velue set in the sibrg register 1 / (n + 1) 1/2 clk polarity reversing circuit 1/2 f1sio 1/8 1/4 f8sio f32sio f2sio pclk1 = 0 pclk1 = 1 smi4 clock source select = 00b = 01b = 10b main clock, pll clock, or on-chip oscillator clock smi6 = 1 smi6 = 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 224 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.38 registers s3c, s4c, s3brg, s4brg, s3trr, and s4trr b7 symbol s3brg s4brg address 0273h 0277h after reset indeterminate indeterminate b0 function rw brgi divides the count source by n + 1 where n = set value 00h to ffh si/oi bit rate register (i = 3, 4) (1, 2, 3) wo setting range notes : 1. write to this register while serial interface is neither transmitting nor receiving. 2. use mov instruction to write to this register. 3. write to this register after setting bits smi1 and smi0 in the sic register. b7 symbol s3trr s4trr address 0270h 0274h after reset indeterminate indeterminate b0 function rw si/oi transmit / receive register (i = 3, 4) (1, 2) setting range notes : 1. write to this register while serial interface is neither transmitting nor receiving. 2. to receive data, set the corresponding port direction bit for sini to 0 (input mode). transmission / reception starts by writing transmit data to this register. after transmission / reception completes, reception data can be read by reading this register. rw b7 b6 b5 b4 b1 b2 b3 symbol s3c s4c address 0272h 0276h after reset 01000000b 01000000b b0 function bit symbol bit name rw si/oi control register (i = 3, 4) (1) rw smi2 souti output disable bit (4) 0 : souti output enabled 1 : souti output disabled (high-impedance) si/oi port select bit rw smi3 0 : input / output port serial interface disabled 1 : souti output, clki function serial interface enabled smi0 smi1 rw internal synchronous clock select bit (6) b1 b0 0 0 : selecting f1sio or f2sio (5) 0 1 : selecting f8sio 1 0 : selecting f32sio 1 1 : do not set rw smi6 synchronous clock select bit 0 : external clock (2) 1 : internal clock (3) rw smi5 transfer direction select bit 0 : lsb first 1 : msb first clk polarity select bit rw smi4 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge rw smi7 souti initial value set bit valid when smi6 = 0 (7) 0 : ?l? output 1 : ?h? output notes : 1. make sure this register is written to by the next instruction after setting the prc2 bit in the prcr register to 1 (write enabled). 2. set the smi3 bit to 1 and the corresponding port direction bit to 0 (input mode). 3. set the smi3 bit to 1 (souti output, clki function). 4. when the smi2 bit is set to 1, the target pin goes to high-impedance state regardless of which function of the pin is being used. 5. selected by the pclk1 bit in the pclkr register. 6. when the values of bits smi1 and smi0 are changed, set the sibrg register. 7. set the value when smi3 bit is set to 0 (i/o port). when the smi3 bit is set to 1 (souti output) subsequently, the selected level signal by the smi7 bit is output from the souti pin. rej09b0392-0064 rev.0.64 oct 12, 2007 page 225 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface figure 17.39 s34c2 register b7 0 0 b6 b5 b4 b1 b2 b3 symbol s34c2 address 0278h after reset 00xxx0x0b b0 function bit symbol bit name rw ? (b1) rw rw ? (b0) ? sm26 si/o 34 control register 2 set to 0 reserved bit no register bit. if necessary, set to 0. read as undefined value note : 1. bits sm26 and sm27 are valid when the sm i3 bit in registers s3c and s4c are set to 1 (sout, clk) ? (b5-b3) rw ? (b2) ? set to 0 reserved bit no register bits. if necessary, set to 0. read as undefined value sout3 output control bit (1) sout3 status after transmission 0 : high-impedance 1 : last bit level retained rw sm27 sout4 output control bit (1) sout4 status after transmission 0 : high-impedance 1 : last bit level retained rej09b0392-0064 rev.0.64 oct 12, 2007 page 226 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface notes: 1. to set the smi6 bit in the sic register to 0 (e xternal clock), follow the procedure described below. ? if the smi4 bit in the sic register = 0, write transmit data to the sitrr register while input on the clki pin is high. the same applies when rewriting the smi7 bit in the sic register. ? if the smi4 bit = 1, write transmit data to the sitrr register while input on the clki pin is low. the same applies when re writing the smi7 bit. ? because shift operation continues as long as the tr ansfer clock is supplied to the si/oi circuit, stop the transfer clock after supplying eight pulses. if th e smi6 bit = 1 (internal clock), the transfer clock automatically stops. 2. unlike uart0 to uart2, si/oi (i = 3 to 4) is not separated between the transf er register and buffer. therefore, do not write the next transmit da ta to the sitrr register during transmission. 3. when the smi6 bit = 1 (internal clock) and bits sm26 (sout3) and sm27 (sout4) in the s34c2 reg- ister = 0 (high-impedance after transmission), souti retains the last data for a 1/2 transfer clock period after completion of transfer and, thereafter, goes to high-impedance state. however, if trans- mit data is written to the sitrr register during this period, souti immediately goes to high-imped- ance state, with the data hold time thereby reduced. 4. when the smi6 bit = 1 (internal clock), the transfer clock stops in the high state if the smi4 bit = 0, or stops in the low state if the smi4 bit = 1. table 17.20 si/o3 and si/o4 specifications item specification transfer data format transfer data length: 8 bits transfer clock ? the smi6 bit in the sic (i = 3, 4) register = 1 (internal clock): fj / (2(n + 1)) fj = f1sio, f8sio, f32sio n = setting value of the sibrg register 00h to ffh ? the smi6 bit = 0 (external clock): input from the clki pin (1) transmission / reception start condition before transmission / reception star ts, satisfy the following requirements write transmit data to the sitrr register (2, 3) interrupt request genera- tion timing ? when the smi4 bit in the sic register = 0 the rising edge of the last transfer clock pulse (4) ? when the smi4 bit = 1 the falling edge of the last transfer clock pulse (4) clki pin function i/o port, transfer clock input, transfer clock output souti pin function i/o port, transmit data output, high-impedance sini pin function i/o port, receive data input select function ? lsb first or msb first selection whether to start sending / receiving data beginning with bit 0 or beginning with bit 7 can be selected ? clk polarity selection whether transmit data is output / input at the risi ng edge or fa lling edge of transfer clock can be selected. ? function for setting an sout i initial value set function when the smi6 bit in the sic register = 0 (external clock), the souti pin output level while not transmitting can be selected. ? souti state selection after transmission whether to set to high-impedance or retain the last bit level can be selected. rej09b0392-0064 rev.0.64 oct 12, 2007 page 227 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.2.1 si/oi operation timing figure 17.40 shows the si/oi operation timing . figure 17.40 si/oi operation timing 17.2.2 clk polari ty selection the smi4 bit in the sic register allo ws selection of the polarity of the transfer clock. figure 17.41 shows the polarity of transfer clock figure 17.41 polarity of transfer clock d7 d0 d1 d2 d3 d4 d5 d6 clki output souti output sini input signal written to sitrr register notes : 1. this diagram applies to the case where the sic register bits are set as follows: smi2 = 0 (souti output), smi3 = 1 (souti output, clki function), smi4 = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) , smi5 = 0 (lsb first) and smi6 = 1 (internal clock) bits sm26 (sout3) and sm27 (sout4) in the s34c2 register are 0 (high-impedance after transmission). 2. if the smi6 bit = 1 (internal clock), the serial i/o starts sending or receiving data a maximum of 0.5 to 1.0 transfer clock cycles after writing to the sitrr register. si/oi internal clock ?0? ?1? ?l? ?h? ?l? ?h? ?l? ?h? ?l? ?h? ir bit in siic register i = 3, 4 0.5 to 1.0 cycle (max.) (2) (2) when the smi4 bit = 1 d1 d2 d3 d4 d5 d6 d7 d1 d2 d3 d4 d5 d6 d7 d0 d0 souti sini clk i (1) when the smi4 bit in the sic register = 0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 souti sini clk i notes: this diagram applies to the case where the sic register bits are set as follows: 1. when the smi5 = 0 (lsb first) and the smi6 = 1 (internal clock) 2. when the smi6 bit =1 (internal clock), high level is output from the clki pin if not transferring data. 3. when the smi6 bit =1 i = 3, 4 rej09b0392-0064 rev.0.64 oct 12, 2007 page 228 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.2.3 functions for setting an souti initial value if the smi6 bit in the sic register = 0 (external cl ock), the souti pin output can be fixed high or low when not transferring. however, the last bit value of the former data is retained between data and data when transmitting data consecutively. figure 17.42 shows the timing chart for setting an souti initial value and how to set it. figure 17.42 souti initial value setting signal written to sitrr register souti (internal) smi7 bit souti pin output smi3 bit setting the souti initial value to ?h? (2) port selection switching (i/o port souti) d0 (i = 3, 4) initial value = ?h? (3) port output d0 (example) when ?h? selected for souti initial value (1) notes: this diagram applies to the case where the bits in the sic register are set as follows: 1. smi2 = 0 (souti output), smi5 = 0 (lsb first) and smi6 = 0 (external clock) 2. souti can only be initialized when input on the clki pin is in the high state if the smi4 bit in the sic register = 0 (transmit data output at the falling edge of the transfer clock) or in the low state if the smi4 bit = 1 (transmit data output at the rising edge of the transfer clock). 3. if the smi6 bit = 1 (internal clock) or if the smi2 bit = 1 (sout output disabled), this output goes to the high-impedance state. set the smi3 bit to 0 (souti pin functions as an i/o port) set the smi7 bit to 1 (souti initial value = ?h?) set the smi3 bit to 1 (souti pin functions as souti output) ?h? level is output from the souti pin write to the sitrr register initial value setting of souti output and starting of transmission / reception serial transmit / reception starts rej09b0392-0064 rev.0.64 oct 12, 2007 page 229 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 17. serial interface 17.2.4 functions for selecting so uti state after transmission if bits sm26 and sm27 in the s34c2 register = 1 (last bit level retained), output from the souti pin retains the last bit level after transmission. figure 17.43 shows the level of sout3 pin after transmis- sion. figure 17.43 level of sout3 pin after transmission sout3 output clk3 output the above sout3 example applies to the case where the sm32 bit in the s3c register = 0 (sout3 output), the sm33 bit in the s3c register = 1 (sout3 output, clk3 selected), the sm34 bit in the s3c register = 0 (trans mit data output at the falling edge and the receive data taken in at the rising edg e of the transfer clock), the sm35 bit in the s3c register = 0 (lsb first), and the sm36 bit in the s3c register = 1 (internal clock) d6 d7 d6 d7 ?h? ?l? ?h? ?l? si/o internal clock when sm26 = 0 (high-impedance) when sm26 = 1 (last bit level retained) rej09b0392-0064 rev.0.64 oct 12, 2007 page 230 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter 18. a/d converter the microcomputer contains one a/d converter circ uit based on 10-bit successive approximation method. the analog inputs share the pins with p10_0 to p10_7, p9_5, p9_6, p0_0 to p0_7, and p2_0 to p2_7. sim- ilarly, adtrg input shares the pin with p9 _7. therefore, when using these inputs, make sure the corre- sponding port direction bits are set to 0 (input mode). when not using the a/d converter, se t the adstby bit to 0 (a/d operation stop: standby), so that no current will flow for the a/d converte r, helping to reduce the po wer consumption of the chip. the a/d conversion result is stored in the adi register for pins ani, an0_i, and an2_i (i = 0 to 7). table 18.1 shows the a/d converter specifications. figure 18.1 shows the a/d converter block diagram, and figures 18.2 and 18.3 show the a/d converter-related registers. notes: 1. set ad frequency as follows: when vcc1 = 4.0 to 5.5 v, 2 mhz ad 25 mhz when vcc1 = 3.2 to 4.0 v, 2 mhz ad 16 mhz when vcc1 = 3.0 to 3.2 v, 2 mhz ad 10 mhz table 18.1 a/d converter specifications item performance a/d conversion method successive approximation analog input voltage (1) 0v to avcc (vcc1) operating clock ad (1) fad, divide-by-2 of fad, divide-by-3 of fa d, divide-by-4 of fad, divide-by-6 of fad, divide-by-12 of fad resolution 10-bit integral nonlinearity error when avcc = vref = 5v an0 to an7 input, an0_0 to an0_7 inpu t or an2_0 to an2_7 input: 3lsb anex0 or anex1 input: 3lsb when avcc = vref = 3.0v an0 to an7 input, an0_0 to an0_7 inpu t or an2_0 to an2_7 input: 3lsb anex0 or anex1 input: 3lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat sweep mode 1 analog input pins 8 pins (an0 to an7) + 2 pins (anex0 and anex1) + 8 pins (an0_0 to an0_7) + 8 pins (an2_0 to an2_7) a/d conversion start condition ? software trigger the adst bit in the adcon0 register is set to 1 (a/d conversion start) ? external trigger (retriggerable) input on the adtrg pin changes state from high to low after the adst bit is set to 1 (a/d conversion start) conversion speed per pin 43 ad cycles minimum rej09b0392-0064 rev.0.64 oct 12, 2007 page 231 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter figure 18.1 a/d converter block diagram anex0 anex1 ch2 to ch0 pm00 pm01 ad0 register (16 bits) data bus (low-order) data bus (high-order) adcon2 register port p10 group port p0 group adgsel1.0 = 00b port p2 group (1) note : 1. port p0 group (an0_0 to an0_7) can be used as analog input pins even when bits pm01 and pm00 are set to 01b (memory expansion mode) and bits pm05 and pm04 are set to 11b (multiplex bus allocated to the entire cs space). an0_0 an0_1 an0_2 an0_3 an0_4 an0_5 an0_6 an0_7 an2_0 an2_1 an2_2 an2_3 an2_4 an2_5 an2_6 an2_7 ad1 register (16 bits) ad2 register (16 bits) ad3 register (16 bits) ad4 register (16 bits) ad5 register (16 bits) ad6 register (16 bits) ad7 register (16 bits) decoder for register decoder for channel selection = 000b = 001b = 010b = 011b = 100b = 101b = 110b = 111b an0 an1 an2 an3 an4 an5 an6 an7 vref vin vref avss adcon0 register adcon1 register successive conver sion register analog circuit pm01 and pm00 = 00b (1) pm01 and pm00 = 00b comparator a/d conversion rate selection 1 cks0 ad cks1 cks2 1 1/2 1/2 adtrg software trigger 0 trg trigger 0 1 0 0 1 0 1 adstby adex1 to adex0 = 01b adex1 to adex0 = 10b anex1.0 = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b ch2 to ch0 adgsel1.0 = 11b = 000b = 001b = 010b = 011b = 100b = 101b = 110b = 111b anex1.0 = 00b = 11b = 11b = 11b = 11b = 11b = 11b = 11b = 00b = 00b = 00b = 00b = 00b = 00b = 00b ch2 to ch0 adgsel1.0 = 10b = 000b = 001b = 010b = 011b = 100b = 101b = 110b = 111b anex1.0 = 00b = 10b = 10b = 10b = 10b = 10b = 10b = 10b = 00b = 00b = 00b = 00b = 00b = 00b = 00b f1 fad fad 1/3 rej09b0392-0064 rev.0.64 oct 12, 2007 page 232 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter figure 18.2 registers adcon0 and adcon1 b7 b6 b5 b4 b1 b2 b3 symbol adcon0 address 03d6h after reset 00000xxxb b0 function bit symbol bit name rw a/d control register 0 (1) note : 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. trg 0 : software trigger 1 : adtrg trigger trigger select bit rw function varies with each operation mode analog input pin select bit ch0 rw ch1 rw ch2 rw adst 0 : a/d conversion stop 1 : a/d conversion start a/d conversion start flag rw cks0 refer to note 3 of the adcon2 register frequency select bit 0 rw md0 rw rw b4 b3 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 or repeat sweep mode 1 a/d operation mode select bit 0 md1 b7 b6 b5 b4 b1 b2 b3 symbol adcon1 address 03d7h after reset 0000x000b b0 function bit symbol bit name rw a/d control register 1 (1) notes: 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. 2. if the adstby bit is changed from 0 (a/d operation stopped) to 1 (a/d operation enabled), wait for 1 ad cycle or more before starting a/d conversion. function varies with each operation mode a/d sweep pin select bit scan0 rw scan1 rw md2 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 a/d operation mode select bit 1 rw cks1 refer to note 3 of the adcon2 registe r frequency select bit 1 rw adstby 0 : a/d operation stopped (standby) 1 : a/d operation enabled a/d standby bit (2) rw function varies with each operation mode extended pin select bit adex0 rw adex1 rw ? (b3) no register bit. if necessary, set to 0. read as undefined value ? rej09b0392-0064 rev.0.64 oct 12, 2007 page 233 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter figure 18.3 registers adcon2 and ad0 to ad7 symbol address after reset rw a/d register (i = 0 to 7) ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 03c1h to 03c0h 03c3h to 03c2h 03c5h to 03c4h 03c7h to 03c6h 03c9h to 03c8h 03cbh to 03cah 03cdh to 03cch 03cfh to 03ceh 000000xxb, xxxxxxxxb 000000xxb, xxxxxxxxb 000000xxb, xxxxxxxxb 000000xxb, xxxxxxxxb 000000xxb, xxxxxxxxb 000000xxb, xxxxxxxxb 000000xxb, xxxxxxxxb 000000xxb, xxxxxxxxb ? note : 1. use the mov instruction to write to this register. function no register bits. if necessary, set to 0. read as undefined value b7 (b8) b0 b0 (b15) b7 0 ro eight low-order bits of a/d conversion result ro two high-order bits of a/d conversion result ro reserved bit set to 0 b7 0 0 0 b6 b5 b4 b1 b2 b3 symbol adcon2 address 03d4h after reset 0000x00xb b0 function bit symbol bit name rw a/d control register 2 (1) notes : 1. if the adcon2 register is rewritten during a/d conversion, the conversion result will be indeterminate. 2. ad frequency is selected by a combination of the cks0 bit in the adcon0 register, the cks1 bit in the adcon1 register, and the cks2 bit in the adcon2 register. ? (b0) no register bit. if necessary, set to 0. read as undefined value ? ? (b7-b5) rw b2 b1 0 0 : select port p10 group 0 1 : do not set 1 0 : select port p0 group 1 1 : select port p2 group a/d input group select bit adgsel0 rw adgsel1 rw ? (b3) no register bit. if necessary, set to 0. read as undefined value ? set to 0 reserved bits rw cks2 0: selects fad, fad divided by 2, or fad divided by 4. 1: selects fad divided by 3, fad divided by 6, or fad divided by 12. frequency select bit 2 (2) cks2 0 0 0 0 1 1 1 1 cks1 0 0 1 1 0 0 1 1 cks0 0 1 0 1 0 1 0 1 ad fad divided by 4 fad divided by 2 fad divided by 6 fad divided by 3 fad fad divided by 12 rej09b0392-0064 rev.0.64 oct 12, 2007 page 234 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter 18.1 mode description 18.1.1 one-shot mode in one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. table 18.2 shows the one-shot mode specifications . figure 18.4 shows the registers adcon0 and adcon1 (one-shot mode). table 18.2 one-shot mode specifications item specification function bits ch2 to ch0 in the adcon0 register and bits adgsel1 and adgsel0 in the adcon2 register, or bits adex1 and adex0 in the adcon1 register select a pin. analog voltage applied to the pin is con- verted to a digital code once. a/d conversion start condi- tion ? when the trg bit in the adcon0 register is 0 (software trigger) the adst bit in the adcon0 register is set to 1 (a/d conversion starts) ? when the trg bit is 1 ( adtrg trigger) input on the adtrg pin changes state from high to low after the adst bit is set to 1 (a/d conversion start) a/d conversion stop condi- tion ? completion of a/d conversion (the adst bit is cleared to 0 (a/d conver- sion stop)) ? set the adst bit to 0 interrupt request genera- tion timing completion of a/d conversion analog input pin select one pin from an0 to an7, an0_0 to an0_7, an2_0 to an2_7, anex0, and anex1 reading of result of a/d converter read one of the registers ad0 to ad7 th at corresponds to the selected pin rej09b0392-0064 rev.0.64 oct 12, 2007 page 235 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter figure 18.4 registers adcon0 and adcon1 (one-shot mode) b7 0 1 b6 b5 b4 b1 b2 b3 symbol adcon1 address 03d7h after reset 0000x000b b0 function bit symbol bit name rw a/d control register 1 (1) notes : 1. if the adcon1 register is rewritten duri ng a/d conversion, the conversi on result will be indeterminate. 2. if the adstby bit is changed from 0 (a/d operation stopped) to 1 (a/d operation enabled), wait for 1 ad cycle or more before starting a/d conversion. invalid in one-shot mode a/d sweep pin select bit scan0 rw scan1 rw md2 set to 0 when one-shot mode is selected a/d operation mode select bit 1 rw cks1 refer to note 3 of the adcon2 registe r frequency select bit 1 rw adstby set to 1 (a/d operation enabled) a/d standby bit (2) rw b7 b6 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a/d converted 1 0 : anex1 input is a/d converted 1 1 : do not set ? (b3) no register bit. if necessary, set to 0. read as undefined value ? extended pin select bit adex0 rw adex1 rw b7 0 0 b6 b5 b4 b1 b2 b3 symbol adcon0 address 03d6h after reset 00000xxxb b0 a/d control register 0 (1) notes : 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. 2. an0_0 to an0_7 and an2_0 to an2_7 can be used in the same way as an0 to an7. use bits adgsel1 and adgsel0 in the adcon2 register to select the desired pin. function rw 0 : software trigger 1 : adtrg trigger rw 0 : a/d conversion stop 1 : a/d conversion start rw refer to note 3 of the adcon2 register rw rw rw rw rw rw b2 b1 b0 0 0 0 : select an0 0 0 1 : select an1 0 1 0 : select an2 0 1 1 : select an3 1 0 0 : select an4 1 0 1 : select an5 1 1 0 : select an6 1 1 1 : select an7 b4 b3 0 0 : one-shot mode bit symbol bit name trg trigger select bit adst a/d conversion start flag cks0 frequency select bit 0 md0 md1 ch0 ch1 ch2 analog input pin select bit (2) a/d operation mode select bit 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 236 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter 18.1.2 repeat mode in repeat mode, analog voltage applied to a selected pi n is repeatedly converted to a digital code. table 18.3 shows the repeat mode specifications. fi gure 18.5 shows the registers adcon0 and adcon1 (repeat mode). table 18.3 repeat mode specifications item specification function bits ch2 to ch0 in the adcon0 register and bits adgsel1 and adgsel0 in the adcon2 register, or bits adex1 and adex0 in the adcon1 register select a pin. analog voltage applied to this pin is repeat- edly converted to a digital code. a/d conversion start condition ? when the trg bit in the adcon0 register is 0 (software trigger) the adst bit in the adcon0 register is set to 1 (a/d conversion start) ? when the trg bit is 1 ( adtrg trigger) input on the adtrg pin changes state from high to low after the adst bit is set to 1 (a/d conversion start) a/d conversion stop condition set the adst bit to 0 (a/d conversion stop) interrupt request generation timing no interrupt requests generated analog input pin select one pin from an0 to an7, an0_0 to an0_7, an2_0 to an2_7, anex0, and anex1 reading of result of a/d converter read one of the registers ad0 to ad7 th at corresponds to the selected pin rej09b0392-0064 rev.0.64 oct 12, 2007 page 237 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter figure 18.5 registers adcon0 and adcon1 (repeat mode) b7 0 1 b6 b5 b4 b1 b2 b3 symbol adcon1 address 03d7h after reset 0000x000b b0 function bit symbol bit name rw a/d control register 1 (1) notes : 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. 2. when the adstby bit is reset from 0 (a/d operation stopped) to 1 (a/d operation enabled), wait for 1 ad cycle or more before starting a/d conversion. invalid in repeat mode a/d sweep pin select bit scan0 rw scan1 rw md2 set to 0 when repeat mode is selected a/d operation mode select bit 1 rw cks1 refer to note 3 of the adcon2 registe r frequency select bit 1 rw adstby set to 1 (a/d operation enabled) a/d standby bit (2) rw b7 b6 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a/d converted 1 0 : anex1 input is a/d converted 1 1 : do not set ? (b3) no register bit. if necessary, set to 0. read as undefined value ? extended pin select bit adex0 rw adex1 rw b7 1 0 b6 b5 b4 b1 b2 b3 symbol adcon0 address 03d6h after reset 00000xxxb b0 a/d control register 0 (1) notes : 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. 2. an0_0 to an0_7, and an2_0 to an2_7 can be used in the same way as an0 to an7. use bits adgsel1 and adgsel0 in the adcon2 register to select the desired pin. function rw 0 : software trigger 1 : adtrg trigger rw 0 : a/d conversion stop 1 : a/d conversion start rw refer to note 3 of the adcon2 register rw rw rw rw rw rw b2 b1 b0 0 0 0 : select an0 0 0 1 : select an1 0 1 0 : select an2 0 1 1 : select an3 1 0 0 : select an4 1 0 1 : select an5 1 1 0 : select an6 1 1 1 : select an7 b4 b3 0 1 : repeat mode bit symbol bit name trg trigger select bit adst a/d conversion start flag cks0 frequency select bit 0 md0 md1 ch0 ch1 ch2 analog input pin select bit (2) a/d operation mode select bit 0 rej09b0392-0064 rev.0.64 oct 12, 2007 page 238 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter 18.1.3 single sweep mode in single sweep mode, analog voltage that is applied to selected pins is conver ted one-by-one to a dig- ital code. table 18.4 shows the single sweep mode specifications. figure 18.6 shows registers adcon0 and adcon1 (single sweep mode). note: 1. an0_0 to an0_7 and an2_0 to an2_7 can be used in the same way as an0 to an7. table 18.4 single sweep mode specifications item specification function bits scan1 and scan0 in the ad con1 register and bits adgsel1 and adgsel0 in the adcon2 register select pins. analog voltage applied to the pins is converted one- by-one to a digital code. a/d conversion start condition ? when the trg bit in the adcon0 register is 0 (software trigger) the adst bit in the adcon0 register is set to 1 (a/d conversion start) ? when the trg bit is 1 ( adtrg trigger) input on the adtrg pin changes state from high to low after the adst bit is set to 1 (a/d conversion start) a/d conversion stop condition ? completion of a/d conversion (the adst bit is cleared to 0 (a/d conver- sion stop)) ? set the adst bit to 0 interrupt request generation timing completion of a/d conversion analog input pin select from an0 and an1 (2 pi ns), an0 to an3 (4 pins), an0 to an5 (6 pins), and an0 to an7 (8 pin) (1) reading of result of a/d converter read one of the registers ad0 to ad7 that corresponds to the selected pin rej09b0392-0064 rev.0.64 oct 12, 2007 page 239 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter figure 18.6 registers adcon0 an d adcon1 (single sweep mode) b7 1 0 b6 b5 b4 b1 b2 b3 symbol adcon0 address 03d6h after reset 00000xxxb b0 a/d control register 0 (1) notes : 1. if the adcon0 register is rewritten duri ng a/d conversion, the conversion result will be indeterminate. 2. an0_0 to an0_7, and an2_0 to an2_7 can be used in the same way as an0 to an7. use bits adgsel1 and adgsel0 in the adcon2 re gister to select the desired pin. function rw 0 : software trigger 1 : adtrg trigger rw 0 : a/d conversion stop 1 : a/d conversion start rw refer to note 3 of the adcon2 register rw rw rw rw rw rw b2 b1 b0 0 0 0 : select an0 0 0 1 : select an1 0 1 0 : select an2 0 1 1 : select an3 1 0 0 : select an4 1 0 1 : select an5 1 1 0 : select an6 1 1 1 : select an7 b4 b3 0 1 : repeat mode bit symbol bit name trg trigger select bit adst a/d conversion start flag cks0 frequency select bit 0 md0 md1 ch0 ch1 ch2 analog input pin select bit (2) a/d operation mode select bit 0 b7 1 1 b6 b5 b4 b1 b2 b3 symbol adcon1 address 03d7h after reset 0000x000b b0 function bit symbol bit name rw a/d control register 1 (1) notes : 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. 2. an0_0 to an0_7 and an2_0 to an2_7 can be used in the same way as an0 to an7. use bits adgsel1 and adgsel0 in the adcon2 register to select the desired pin. 3. if the adstby bit is changed from 0 (a/d operation stopped) to 1 (a/d operation enabled), wait for 1 ad cycle or more before starting a/d conversion. cks1 refer to note 3 of the adcon2 register frequency select bit 1 rw b7 b6 0 0 : anex0 and anex1 are not used 0 1 : do not set 1 0 : do not set 1 1 : do not set ? (b3) no register bit. if necessary, set to 0. read as undefined value ? extended pin select bit adex0 rw adex1 rw md2 1 : repeat sweep mode 1 a/d operation mode select bit 1 rw when repeat sweep mode 1 is selected b1 b0 0 0 : an0 (1 pin) 0 1 : an1 (2 pins) 1 0 : an2 (3 pins) 1 1 : an3 (4 pins) a/d sweep pin select bit (2) scan0 rw scan1 rw adstby set to 1 (a/d operation enabled) a/d standby bit (3) rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 240 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter 18.1.4 repeat sweep mode 0 in repeat sweep mode 0, analog voltage applied to sele cted pins is repeatedly converted to a digital code. table 18.5 shows the repeat sweep mode 0 spec ifications. figure 18.7 shows registers adcon0 and adcon1 (repeat sweep mode 0). note: 1. an0_0 to an0_7 and an2_0 to an2_7 can be used in the same way as an0 to an7. table 18.5 repeat sweep mode 0 specifications item specification function bits scan1 and scan0 in the ad con1 register and bits adgsel1 and adgsel0 in the adcon2 register select pins. analog voltage applied to the pins is repeatedly conv erted to a digital code. a/d conversion start condition ? when the trg bit in the adcon0 register is 0 (software trigger) the adst bit in the adcon0 register is set to 1 (a/d conversion start) ? when the trg bit is 1 ( adtrg trigger) input on the adtrg pin changes state from high to low after the adst bit is set to 1 (a/d conversion start) a/d conversion stop condition set the adst bit to 0 (a/d conversion stop) interrupt request generation timing no interrupt requests generated analog input pin select from an0 and an1 (2 pi ns), an0 to an3 (4 pins), an0 to an5 (6 pins), and an0 to an7 (8 pin) (1) reading of result of a/d converter read one of the registers ad0 to ad7 that corresponds to the selected pin rej09b0392-0064 rev.0.64 oct 12, 2007 page 241 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter figure 18.7 registers adcon0 and adcon1 (repeat sweep mode 0) b7 1 1 b6 b5 b4 b1 b2 b3 symbol adcon0 address 03d6h after reset 00000xxxb b0 function bit symbol bit name rw a/d control register 0 (1) note : 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. trg 0 : software trigger 1 : adtrg trigger trigger select bit rw invalid in repeat sweep mode 0 analog input pin select bit ch0 rw ch1 rw ch2 rw adst 0 : a/d conversion stop 1 : a/d conversion start a/d conversion start flag rw cks0 refer to note 3 of the adcon2 register frequency select bit 0 rw md0 rw rw b4 b3 1 1 : repeat sweep mode 0 or repeat sweep mode 1 a/d operation mode select bit 0 md1 b7 0 1 b6 b5 b4 b1 b2 b3 symbol adcon1 address 03d7h after reset 0000x000b b0 function bit symbol bit name rw a/d control register 1 (1) notes : 1. if the adcon1 register is rewritten duri ng a/d conversion, the conversi on result will be indeterminate. 2. an0_0 to an0_7 and an2_0 to an2_7 can be used in the same way as an0 to an7. use bits adgsel1 and adgsel0 in the adcon2 register to select the desired pin. 3. if the adstby bit is changed from 0 (a/d operation stopped) to 1 (a/d operation enabled), wait for 1 ad cycle or more before starting a/d conversion. cks1 refer to note 3 of the adcon2 register frequency select bit 1 rw adstby set to 1 (a/d operation enabled) a/d standby bit (3) rw b7 b6 0 0 : anex0 and anex1 are not used 0 1 : do not set 1 0 : do not set 1 1 : do not set ? (b3) no register bit. if necessary, set to 0. read as undefined value ? extension pin select bit adex0 rw adex1 rw md2 set to 0 when repeat sweep mode 0 is selected a/d operation mode select bit 1 rw when repeat sweep mode 0 is selected b1 b0 0 0 : an0 to an1 (2 pins) 0 1 : an0 to an3 (4 pins) 1 0 : an0 to an5 (6 pins) 1 1 : an0 to an7 (8 pins) a/d sweep pin select bit (2) scan0 rw scan1 rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 242 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter 18.1.5 repeat sweep mode 1 in repeat sweep mode 1, analog voltage selectively ap plied to all pins is repeatedly converted to a digi- tal code. table 18.6 shows the repeat sweep mode 1 specifications. figure 18.8 shows registers adcon0 and adcon1 (repeat sweep mode 1). notes: 1. an0_0 to an0_7 and an2_0 to an2_7 can be used in the same way as an0 to an7. table 18.6 repeat sweep mode 1 specifications item specification function the input voltages on all pins selected by bits adgsel1 and adgsel0 in the adcon2 register are a/d converted repeatedly, with priority given to pins selected by bits scan1 and scan0 in the adcon1 register and bits adgsel1 and adgsel0. example: if an0 selected, input volt ages are a/d converted in order of an0 an1 an0 an2 an0 an3, and so on. a/d conversion start condition ? when the trg bit in the adcon0 re gister is 0 (software trigger), the adst bit in the adcon0 register is set to 1 (a/d conversion start) ? when the trg bit is 1 ( adtrg trigger), input on the adtrg pin changes state from high to low after the adst bit is set to 1 (a/d conversion start) a/d conversion stop condition set the adst bit to 0 (a/d conversion stop) interrupt request generation timing no interrupt requests generated analog input pins to be given priority when a/d converted select from an0 (1 pin), an0 and an 1 (2 pins), an0 to an2 (3 pins), and an0 to an3 (4 pins) (1) reading of result of a/d converter read one of the registers ad0 to ad7 that corresponds to the selected pin rej09b0392-0064 rev.0.64 oct 12, 2007 page 243 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter figure 18.8 registers adcon0 and adcon1 (repeat sweep mode 1) b7 1 1 b6 b5 b4 b1 b2 b3 symbol adcon0 address 03d6h after reset 00000xxxb b0 function bit symbol bit name rw a/d control register 0 (1) note : 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. trg 0 : software trigger 1 : adtrg trigger trigger select bit rw invalid in repeat sweep mode 1 analog input pin select bit ch0 rw ch1 rw ch2 rw adst 0 : a/d conversion stop 1 : a/d conversion start a/d conversion start flag rw cks0 refer to note 3 of the adcon2 register frequency select bit 0 rw md0 rw rw b4 b3 1 1 : repeat sweep mode 0 or repeat sweep mode 1 a/d operation mode select bit 0 md1 b7 1 1 b6 b5 b4 b1 b2 b3 symbol adcon1 address 03d7h after reset 0000x000b b0 function bit symbol bit name rw a/d control register 1 (1) notes : 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. 2. an0_0 to an0_7 and an2_0 to an2_7 can be used in the same way as an0 to an7. use bits adgsel1 and adgsel0 in the adcon2 register to select the desired pin. 3. if the adstby bit is changed from 0 (a/d operation stopped) to 1 (a/d operation enabled), wait for 1 ad cycle or more before starting a/d conversion. cks1 refer to note 3 of the adcon2 register frequency select bit 1 rw b7 b6 0 0 : anex0 and anex1 are not used 0 1 : do not set 1 0 : do not set 1 1 : do not set ? (b3) no register bit. if necessary, set to 0. read as undefined value ? extended pin select bit adex0 rw adex1 rw md2 1 : repeat sweep mode 1 a/d operation mode select bit 1 rw when repeat sweep mode 1 is selected b1 b0 0 0 : an0 (1 pin) 0 1 : an1 (2 pins) 1 0 : an2 (3 pins) 1 1 : an3 (4 pins) a/d sweep pin select bit (2) scan0 rw scan1 rw adstby set to 1 (a/d operation enabled) a/d standby bit (3) rw rej09b0392-0064 rev.0.64 oct 12, 2007 page 244 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter 18.2 conversion rate the conversion rate is defined as follows. start dummy time depends on which ad is selected. table 18.7 shows start dummy time. when the adst bit in the adcon0 register is set to 1 (a/d conversion start), a/d conversion starts after start dummy time elapses. 0 (a/d conversion stop) is read if the adst bit is read before a/d conversion starts. for multiple pins or a/d conversion repeat mode, for each pin, between-execution dummy time is inserted between a/d conversion execution time and the next a/d conversion execution time. the adst bit is set to 0 during the end dummy time, an d the last a/d conversion result is set to the adi register in one-shot mode and single sweep mode. while in one-shot mode: start dummy time + a/d conversion execution time + end dummy time when two pins are selected while in single sweep mode: start dummy time + (a/d conversion execution time + between-execution dummy time + a/d conversion execution time) + end dummy time start dummy time: see table 18.7 ?start dummy time? a/d conversion execution time: 40 ad cycles per pin between-execution dummy time: 1 ad cycle end dummy time: 2 to 3 cycles of fad 18.3 extended analog input pins in one-shot and repeat modes, pins anex0 and an ex1 can be used as analog input pins. use bits adex1 and adex0 in the adcon1 register to se lect whether or not to use anex0 and anex1. the a/d conversion results of anex0 and anex1 inputs are stored in registers ad0 and ad1, respec- tively. 18.4 current consumption reducing function when not using the a/d converter, power consumption can be reduced by setting the adstby bit in the adcon1 register to 0 (a/d operation stopped: sta ndby) to shut off any analog circuit current flow. to use the a/d converter, set the adstby bit to 1 (a/d operation enabled) af ter operating longer than one cycle of a timer count source, and then set the ad st bit in the adcon0 register to 1 (a/d conversion start). do not set bits adst an d adstby to 1 at the same time. also, do not set the adstby bit to 0 (a/d operat ion stopped: standby) during a/d conversion. table 18.7 start dummy time ad selection sta rt dummy time fad 1 to 2 cycles of fad fad divided by 2 2 to 3 cycles of fad fad divided by 3 3 to 4 cycles of fad fad divided by 4 3 to 4 cycles of fad fad divided by 6 4 to 5 cycles of fad fad divided by 12 7 to 8 cycles of fad rej09b0392-0064 rev.0.64 oct 12, 2007 page 245 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 18. a/d converter 18.5 output impedance of se nsor under a/ d conversion figure 18.9 analog input pin and exte rnal sensor equivalent circuit r0 r (10.0 kw) c (10.0 pf) vin microcomputer sensor equivalent circuit vc sampling time 15 ? ad rej09b0392-0064 rev.0.64 oct 12, 2007 page 246 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 19. d/a converter 19. d/a converter 19.1 summary the d/a converter consists of two indep endent 8-bit r-2r ty pe d/a converters. d/a conversion is performed by writing to the dai register (i = 0 to 1). to output the result of conversion, set the daie bit in the dacon regist er to 1 (output enabled). before using d/a conversion, clear the cor- responding port direction bit to 0 (input mode). when t he daie bit is set to 1 (input enabled), pull-up of a corresponding port is disabled. output analog voltage (v) is determined by a set value (n: decimal) in the dai register. v = vref (n = 0 to 255) vref: reference voltage table 19.1 lists the d/a converter performance. figure 19.1 shows the d/a converter block diagram. figure 19.2 shows registers dacon, da0, and da1. figure 19.3 shows the d/a converter equivalent circuit. figure 19.1 d/a converter block diagram table 19.1 d/a conv erter performance item performance d/a conversion method r-2r resolution 8 bits analog output pin 2 channels (da0 and da1) n 256 --------- - da0 register r-2r resistor ladder da0e bit da0 low-order bits of data bus da1 register r-2r resistor ladder da1e bit da1 0 1 0 1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 247 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 19. d/a converter figure 19.2 registers dacon, da0, and da1 figure 19.3 d/a converter equivalent circuit b7 b6 b5 b4 b1 b2 b3 d/a control register (1) symbol dacon address 03dch bit symbol bit name rw da0e after reset 00h b0 function d/a 0 output enable bit da1e d/a 1 output enable bit 0 : output disabled 1 : output enabled rw rw 0 : output disabled 1 : output enabled ? (b7-b2) no register bits. if necessary, set to 0. read as 0 ? note : 1. when not using the d/a converter, clear the daie bit (i = 0 to 1) to 0 (output disabled) to reduce the unnecessary current consumption in the chip and set the dai register to 00h to prevent current from flowing into the r-2r resistor ladder. b7 symbol da0 da1 address 03d8h 03dah after reset 00h 00h b0 function rw output value of d/a conversion 00h to ffh d/ai register (i = 0 to 1) (1) rw setting range note : 1. when not using the d/a converter, clear the daie bit (i = 0 to 1) to 0 (output disabled) to reduce the unnecessary current consumption in the chip and set the dai register to 00h to prevent current from flowing into the r-2r resistor ladder. v ref (2) avss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r daie bit dai 1 0 1 0 msb lsb dai register notes: 1. the above diagram applies when the dai register is set to 2ah. 2. vref is not related to adstby bit in the ad0con1 register. r i = 0 to 1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 248 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 20. crc operation 20. crc operation the cyclic redundancy check (crc) operation detects an error in data blocks. the microcomputer uses a generator polynomial of crc_ccitt (x 16 + x 12 + x 5 + 1) to generate crc code. the crc code consists of 16 bits which are generated fo r each data block in given length, separated in 8 bit units. after the initial val ue is set in the crcd register, the crc code is set in that register each time one byte of data is written to the crcin register. crc code generation for one-byte data is finished in two cycles. figure 20.1 shows the crc circuit block diagra m. figure 20.2 shows registers crcd and crcin. figure 20.3 shows an example using the crc operation. figure 20.1 crc circuit block diagram figure 20.2 registers crcd and crcin eight low-order bits eight high-order bits data bus (high-order) data bus (low-order) crcd register crcin register crc code generating circuit x 16 + x 12 + x 5 + 1 b7 symbol crcd address 03bdh to 03bch after reset indeterminate b0 function rw when data is written to the crcin register after setting the initial value in the crcd register, the crc code can be read out from the crcd register. 0000h to ffffh crc data register rw setting range b7 b0 (b8) (b15) b7 symbol crcin address 03beh after reset indeterminate b0 function rw data input 00h to ffh crc input register rw setting range rej09b0392-0064 rev.0.64 oct 12, 2007 page 249 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 20. crc operation figure 20.3 crc operation b15 b0 (2) write 0000h (initial value) b0 b7 b15 b0 (3) write 01h two cycles later, the crc code for 80h, i.e., 9188h, has its bit positions reversed to become 1189h which is stored in the crcd register. 1189h b0 b7 b15 b0 (4) write 23h 0a41h 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1 ? setting procedure (1) reverse the bit positions of the value ?80c4h? by program in 1-byte units. 80h 01h, c4h 23h two cycles later, the crc code for 80c4h, i.e., 8250h, has its bit positions reversed to become 0a41h which is stored in the crcd register. as shown in (3) above, bit position of 01h (00000001b) wri tten to the crcin register is reversed and becomes 10000000b. add 1000 0000 0000 0000 0000 0000b, as 10000000b plus 16 digits, to 0000 0000 0000 0000 0000 0000b, as 0000 0000 0000 0000b plus 8 digits as the default value of the crcd register to perform the modulo-2 division. generator polynomial crc code data ? details of crc operation 0001 0001 1000 1001b (1189h), the remainder 1001 0001 1000 1000b (9188h) with inversed bit position, can be read from the crcd register. when going on to (4) above, 23h (00100011b) written in the crcin register is reversed and becomes 11000100b. add 1100 0100 0000 0000 0000 0000b, as 11000100b plus 16 digits, to 1001 0001 1000 1000 0000 0000b, as 1001 0001 1000 1000b plus 8 digits as a remainder of (3) left in t he crcd register to perform the modulo-2 division. 0000 1010 0100 0001b (0a41h), the remainder with reversed bit position, can be read from the crcd register. ? crc operation performed by the m16c crc code : remainder of a division in which the value written to the crcin register with its bit positions reversed is divided by the generator polynomial generator polynomial : x 16 + x 12 + x 5 + 1 (1 0001 0000 0010 0001b) setup procedure and crc operation when generating crc code ?80c4h? crcd register crcin register crcd register crcin register crcd register rej09b0392-0064 rev.0.64 oct 12, 2007 page 250 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports 21. programmable i/o ports 88 programmable input / output ports (i/o ports) are av ailable. the direction r egisters determine individual port status, input or output. the pull-up control regist ers determine whether the pots, divided into groups of four ports, are pulled up or not. p8_5 is an input port and no pull-up is allowed. port p8_5 shares the pin with nmi , so that the nmi input level can be read from the p8_5 bit in the p8 register. figures 21.1 to 21.5 show the i/o po rts. figure 21.6 shows the i/o pins. each pin functions as an i/o port, a peripheral function input / output, or a bus control pin. to set peripheral functions, refer to the description for individual functions. if any pin is used as a peripheral function input or d/a converter output pin, set the direction bit of the corresponding pin to 0 (input mode). any pin used as an output pin for peripheral function s other than the d/a converter is directed for output no matter how the corresponding direction bit is set. to use as bus control pins, refer to 8.2 ?bus control? . p0 to p5 are capable of vcc2-level input / output; p6 to p10 are capable of vcc1- level input / output. 21.1 port pi direction register (pdi register, i = 0 to 10) figure 21.7 shows the pi direction registers. this register selects whether the i/o port is to be used for input or output. each bit in the pdi register cor- responds to one port. during memory extension or microprocessor mode, th e pdi registers for the pins functioning as bus con- trol pins (a0 to a19, d0 to d15, cs0 to cs3 , rd , wrl / wr , wrh / bhe , ale, rdy , hold , hlda , and bclk) cannot be modified. 21.2 port pi register (p i register, i = 0 to 10) figure 21.8 shows the pi registers. data input / output to and from external devices are accomplished by reading and writing to the pi regis- ter. each bit of the pi register consists of a port latch to hold the output data and a circuit to read the pin sta- tus. for ports set for input mode, the input level of the pin can be read by reading the corresponding pi regis- ter, and data can be written to the port latch by writing to the pi register. for ports set for output mode, the port latch can be read by reading the corresponding pi register, and data can be written to the port latch by writing to the pi register. the data written to the port latch is output from the pin. each bit in the pi register correspond to each port. during memory extension or microprocessor mode, the pi registers for the pins functioning as bus control pins (a0 to a19, d0 to d15, cs0 to cs3 , rd , wrl / wr , wrh / bhe , ale, rdy , hold , hlda , and bclk) cannot be modified. 21.3 pull-up control register 0 to pull-u p control register 2 (registers pur0 to pur2) figures 21.9 and 21.10 show the registers pur0 to pur2. bits in registers pur0 to pur2 can be used to select whether or not to pull the corresponding port high in 4 pin units. the port chosen to be pulled high has a pull- up resistor connected to it when the direction bit is set for input mode. however, the pull-up control register has no effect on p0 to p3, p4_0 to p4_3, and p5 during memory extension or microprocessor mode. although the regist er contents can be modified, no pull-up resistors are connected. 21.4 port control regist er (pcr register) figure 21.11 shows the pcr register. when the p1 register is read after setting the pcr0 bit in the pcr register to 1, the corresponding port latch can be read no matter how the pd1 register is set. rej09b0392-0064 rev.0.64 oct 12, 2007 page 251 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports figure 21.1 i/o ports (1) p1_1 to p1_3 p1_0 p0_0 to p0_7, p2_0 to p2_3, p2_6 to p2_7, p10_0 to p10_3 p3_0 to p3_7, p4_0 to p4_3, p5_0 to p5_4, p5_6 (dotted section included) (dotted section not included) note: 1. symbolizes a parasitic diode. make sure the input voltage on each port will never exceed vcc. vcc: vcc1 for ports p6 to p10, and vcc2 for ports p0 to p5. data bus pull-up selection (note 1) analog input direction register port latch data bus (note 1) cmos / nch selection pull-up selection direction register port latch port p1 control register 1 output port p1 control register data bus port latch (note 1) 1 output pull-up selection direction register rej09b0392-0064 rev.0.64 oct 12, 2007 page 252 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports figure 21.2 i/o ports (2) p4_4, p5_7, p6_0, p6_4, p7_3 to p7_5, p8_1, p9_0, p9_2 (note 1) p2_4, p2_5 p10_4 to p10_7 p1_4 (dotted section not included) p1_5 to p1_7 (dotted section included) input to respective peripheral functions port p1 control register data bus pull-up selection (note 1) analog input (note 1) input to respective peripheral functions port control register input to respective peripheral functions output 1 pull-up selection pull-up selection direction register direction register direction register port latch port latch port latch data bus data bus note: 1. symbolizes a parasitic diode. make sure the input voltage on each port will never exceed vcc. vcc: vcc1 for ports p6 to p10, and vcc2 for ports p0 to p5. rej09b0392-0064 rev.0.64 oct 12, 2007 page 253 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports figure 21.3 i/o ports (3) p4_5 to p4_7, p6_1 to p6_3, p6_5 to p6_7, p7_2, p7_6 to p7_7, p8_0 pull-up selection data bus port latch output 1 input to respective peripheral functions (note 1) cmos / nch selection p7_0, p7_1 input to respective peripheral functions output 1 (note 1) p5_5, p8_2 to p8_4, p9_1, p9_7 input to respective peripheral functions (note 1) note: 1. symbolizes a parasitic diode. make sure the input voltage on each port will never exceed vcc. vcc: vcc1 for ports p6 to p10, and vcc2 for ports p0 to p5. pull-up selection direction register direction register direction register port latch port latch data bus data bus rej09b0392-0064 rev.0.64 oct 12, 2007 page 254 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports figure 21.4 i/o ports (4) p8_5 data bus port latch (note 1) nmi enabled nmi enabled sd input nmi interrupt input p9_3, p9_4 port latch pull-up selection analog output d/a output enabled d/a output enabled input to respective peripheral functions (note 1) port latch output 1 input to respective peripheral functions analog input (note 1) p9_5 (inside dotted-line included) p9_6 (inside dotted-line not included) note: 1. symbolizes a parasitic diode. make sure the input voltage on each port will never exceed vcc. vcc: vcc1 for ports p6 to p10, and vcc2 for ports p0 to p5. data bus data bus direction register direction register direction register pull-up selection rej09b0392-0064 rev.0.64 oct 12, 2007 page 255 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports figure 21.5 i/o ports (5) figure 21.6 i/o pins note: 1. symbolizes a parasitic diode. make sure the input voltage on each port will never exceed vcc. vcc: vcc1 for ports p6 to p10, and vcc2 for ports p0 to p5. p8_7 data bus port latch pull-up selection (note 1) p8_6 port latch output 1 (note 1) fc rf rd data bus pull-up selection direction register direction register byte byte signal input (note 1) cnvss cnvss signal input (note 1) reset reset signal input (note 1) note: 1. symbolizes a parasitic diode. make sure the input voltage on each port will never exceed vcc1. rej09b0392-0064 rev.0.64 oct 12, 2007 page 256 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports figure 21.7 registers pd0 to pd10 b7 b6 b5 b4 b1 b2 b3 port pi direction regi ster (i = 0 to 10) (1, 2) symbol pd0 to pd3 pd4 to pd7 pd8 pd9, pd10 address 03e2h, 03e3h, 03e6h, 03e7h 03eah, 03ebh, 03eeh, 03efh 03f2h 03f3h, 03f6h after reset 00h 00h 00h 00h b0 bit symbol bit name rw function pdi_0 port pi_0 direction bit 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) rw pdi_1 port pi_1 direction bit rw pdi_2 port pi_2 direction bit rw pdi_3 port pi_3 direction bit rw pdi_4 port pi_4 direction bit rw pdi_5 port pi_5 direction bit rw pdi_6 port pi_6 direction bit rw pdi_7 port pi_7 direction bit rw notes : 1. make sure the pd9 register is written following the instruction to set the prc2 bit in the prcr register to 1 (write enabled). 2. during memory extension and microprocessor modes, the pdi register for the pins functioning as bus control pins (a0 to a19, d0 to d15, cs0 to cs3, rd, wrl / wr, wrh / bhe, ale, rdy, hold, hlda and bclk) cannot be modified. rej09b0392-0064 rev.0.64 oct 12, 2007 page 257 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports figure 21.8 registers p0 to p10 b7 b6 b5 b4 b1 b2 b3 port pi register (i = 0 to 10) (2) symbol p0 to p3 p4 to p7 p8 p9, p10 address 03e0h, 03e1h, 03e4h, 03e5h 03e8h, 03e9h, 03ech, 03edh 03f0h 03f1h, 03f4h after reset indeterminate indeterminate indeterminate indeterminate b0 bit symbol bit name rw function pi_0 port pi_0 bit the pin level on any i/o port which is set for input mode can be read by reading the corresponding bit in this register. the pin level on any i/o port which is set for output mode can be controlled by writing to the corresponding bit in this register 0 : ?l? level 1 : ?h? level (1) rw pi_1 port pi_1 bit rw pi_2 port pi_2 bit rw pi_3 port pi_3 bit rw pi_4 port pi_4 bit rw pi_5 port pi_5 bit rw pi_6 port pi_6 bit rw pi_7 port pi_7 bit rw notes : 1. since p7_0, p7_1, and p8_5 are n-channel open drain ports, the pin status becomes high-impedance. 2. during memory extension and microprocessor modes, the pi register for the pins functioning as bus control pins (a0 to a19, d0 to d15, cs0 to cs3, rd, wrl / wr, wrh / bhe, ale, rdy, hold, hlda and bclk) cannot be modified. rej09b0392-0064 rev.0.64 oct 12, 2007 page 258 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports figure 21.9 registers pur0 and pur1 b7 b6 b5 b4 b1 b2 b3 pull-up control register 0 (1) symbol pur0 address 0360h bit symbol bit name rw after reset 00h b0 function pu00 p0_0 to p0_3 pull-up 0 : not pulled high 1 : pulled high (2) rw pu01 p0_4 to p0_7 pull-up rw pu02 p1_0 to p1_3 pull-up rw pu03 p1_4 to p1_7 pull-up rw pu04 p2_0 to p2_3 pull-up rw pu05 p2_4 to p2_7 pull-up rw pu06 p3_0 to p3_3 pull-up rw pu07 p3_4 to p3_7 pull-up rw notes : 1. during memory extension or micropro cessor mode, the corresponding register contents can be modified, but the pins are not pulled high. 2. the pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. b7 b6 b5 b4 b1 b2 b3 pull-up control register 1 symbol pur1 address 0361h bit symbol rw after reset (5) 00000000b b0 function pu10 0 : not pulled high 1 : pulled high (3) rw pu11 rw pu12 rw pu13 rw pu14 rw pu15 rw pu16 rw pu17 rw 00000010b notes : 1. pins p7_0 and p7_1 do not have pull-ups. 2. during memory extension and microprocessor modes, the pins are not pulled high although the contents of these bits can be modified. 3. to enable the pull-up registers, the corresponding bit in the register should be set to 1 (pulled high) and the respective bits in the direction register should be set to 0 (input mode). 4. if bits pm01 to pm00 in the pm0 register are set to 01b (memory expansion mode) or 11b (microprocessor mode) in a program during single-chip mode, the pu11 bit becomes 1. 5. the values after hardware reset 1 or brown-out reset is as follows: ? 00000000b when input on cnvss pin is ?l? ? 00000010b when input on cnvss pin is ?h? the values after software reset, watchdog timer reset, and oscillation stop detection reset are as follows: ? 00000000b when bits pm01 to pm00 are 00b (single-chip mode) ? 00000010b when bits pm01 to pm00 are 01b (memory expansion mode) or 11b (microprocessor mode) bit name p4_0 to p4_3 pull-up (2) p4_4 to p4_7 pull-up (4) p5_0 to p5_3 pull-up (2) p5_4 to p5_7 pull-up (2) p6_0 to p6_3 pull-up p6_4 to p6_7 pull-up p7_2 to p7_3 pull-up (1) p7_4 to p7_7 pull-up rej09b0392-0064 rev.0.64 oct 12, 2007 page 259 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports figure 21.10 pur2 register figure 21.11 pcr register b7 b6 b5 b4 b1 b2 b3 pull-up control register 2 symbol pur2 address 0362h bit symbol rw after reset 00h b0 function notes : 1. to enable the pull-up registers, the corresponding bit in the register should be set to 1 (pulled high) and the respective bits in the direction register should be set to 0 (input mode). 2. the p8_5 pin does not have pull-up. pu20 0 : not pulled high 1 : pulled high (1) rw pu21 rw pu22 rw pu23 rw pu24 rw pu25 rw ? (b7-b6) no register bits. if necessary, set to 0. read as 0 ? bit name p8_0 to p8_3 pull-up p8_4 to p8_7 pull-up (2) p9_0 to p9_3 pull-up p9_4 to p9_7 pull-up p10_0 to p10_3 pull-up p10_4 to p10_7 pull-up b7 b6 b5 b4 b1 b2 b3 port control register symbol pcr address 0366h bit symbol rw after reset 00000xx0b b0 notes : 1. to use the an2_4 pin as an analog input pin, set the pcr5 bit to 1 (int6 input disabled). 2. to use the an2_5 pin as an analog input pin, set the pcr6 bit to 1 (int7 input disabled). 3. to use pins an4 to an7 as analog input pins, set the pcr7 bit to 1 (key input disabled). bit name function pcr0 rw no register bits. if necessary, set to 0. read as 0 ? (b4-b1) ? pcr5 rw pcr6 rw pcr7 rw int6 input enable bit (1) int7 input enable bit (2) key input enable bit (3) 0 : enabled 1 : disabled 0 : enabled 1 : disabled 0 : enabled 1 : disabled port p1 control bit operation performed when the p1 register is read 0 : when the port is set for input, the input levels of pins p1_0 to p1_7 are read. when set for output, the port latch is read. 1 : the port latch is read regardless of whether the port is set for input or output. rej09b0392-0064 rev.0.64 oct 12, 2007 page 260 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports notes: 1. when setting the port for output mode and leave it open, be aware that the port remains in input mode until it is switched to output mode in a program after reset. for this reason, the voltage level on the pin becomes indeterminate, causing the power supply current to increase while the port remains in input mode. 2. furthermore, by considering a poss ibility that the contents of the direction registers could be changed by noise or noise-induced loss of control, it is recommended that the contents of the direction regis- ters be regularly reset in software to improve reliability of the program. 3. make sure the unused pins are processed with th e shortest possible wiring from the microcomputer pins (within 2 cm). 4. when the ports p7_0, p7_1, and p8_5 are set for output mode, make sure a low-level signal is out- put from the pins. 5. the ports p7_0, p7_1, and p8_5 are n-channel open-drain outputs. 6. this applies when external clock is input to the xin pin or when vcc1 is connected to via a resistor. table 21.1 unassigned pin ha ndling in single-chip mode pin name connection (2) ports p0 to p5 one of the followings: set for input mode and connect a pi n to vss via resistor (pull-down) set for input mode and connect a pin to vcc2 via resistor (pull-up) set for output mode and leave the pins open (1) ports p6 to p10 one of the followings: set for input mode and connect a pi n to vss via resistor (pull-down) set for input mode and connect a pin to vcc1 via resistor (pull-up) set for output mode and leave the pins open (1, 3) xout (4) open xin connect to vcc1 (pull-up) via resistor avcc, vref connect to vcc1 avss, byte connect to vss rej09b0392-0064 rev.0.64 oct 12, 2007 page 261 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports notes: 1. when setting the port for output mode and leave it open, be aware that the port remains in input mode until it is switched to output mode in a program after reset. for this reason, the voltage level on the pin becomes indeterminate, causing the power supply current to increase while the port remains in input mode. 2. furthermore, by considering a poss ibility that the contents of the direction registers could be changed by noise or noise-induced loss of control, it is recommended that the contents of the direction regis- ters be regularly reset in software to improve reliability of the program. 3. make sure the unused pins are processed with th e shortest possible wiring from the microcomputer pins (within 2 cm). 4. if the cnvss pin has the vss level applied to it, th ese pins are set for input ports until the processor mode is switched over in a program after reset. for this reason, the voltage levels on these pins become indeterminate, causing the power supply curr ent to increase while they remain set for input ports. 5. when the ports p7_0, p7_1, and p8_5 are set for output mode, make sure a low-level signal is out- put from the pins. 6. the ports p7_0, p7_1, and p8_5 are n-channel open-drain outputs. 7. this applies when external clock is input to the xin pin or when vcc1 is connected to via a resistor. 8. if the pm07 bit in the pm0 register is set to 1 (b clk not output), connect this pin to vcc2 via a resis- tor (pulled high). table 21.2 unassigned pin handling in memory expansion mode and microprocessor mode pin name connection (2) ports p0 to p5 one of the followings: set for input mode and connect a pi n to vss via resistor (pull-down) set for input mode and connect a pin to vcc2 via resistor (pull-up) set for output mode and leave the pins open (1, 3) ports p6 to p10 one of the followings: set for input mode and connect a pi n to vss via resistor (pull-down) set for input mode and connect a pin to vcc1 via resistor (pull-up) set for output mode and leave the pins open (1, 4) bhe , ale, hlda , xout (5) , bclk (6) open hold , rdy connect to vcc2 (pull-up) via resistor xin connect to vcc1 (pull-up) via resistor avcc, vref connect to vcc1 avss connect to vss rej09b0392-0064 rev.0.64 oct 12, 2007 page 262 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 21. programmable i/o ports figure 21.12 unassigned pin handling port p0 to p10 xin xout avcc byte avss vref microcomputer vcc1 vss in single-chip mode port p6 to p10 xin xout avcc avss vref open microcomputer vcc2 in memory expansion mode or in microprocessor mode hold rdy ale bclk (1) bhe hlda open (input mode) . . . (input mode) (output mode) open (input mode) . . . (input mode) (output mode) open . . . . . . vss port p4_5 / cs1 to p4_7 / cs3 note: 1. if the pm07 bit in the pm0 register is set to 1 (bclk not output), connect this pin to vcc2 via a resistor (pulled high). vcc1 vcc2 vcc1 vcc1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 263 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22. flash memory version the flash memory can perform in three rewrite m odes: cpu rewrite mode, st andard serial i/o mode, and parallel i/o mode. table 22.1 lists specifications of t he flash memory version. see tables 1.1 and 1.2 spec- ifications overview for the items not listed in table 22.1. note: 1. definition of program and erase endurance the program and erase endurance refers to the number of per-block erasures. for example, assume a case where a 4 kbyte block is programmed in 1,024 operations, writing two words at a time, and erased thereafter. in this case, the block is reckoned as having been programmed and erased once. if the program and erase endurance is 100 times, each block can be erased up to 100 times. notes: 1. the pm13 bit remains set to 1 while the fmr01 bit in the fmr0 register = 1 (cpu rewrite mode enabled). the pm13 bit is reverted to its original value by clearing the fmr01 bit to 0 (cpu rewrite mode disabled). however, if the pm13 bit is changed during cpu rewrite mode, its changed value is not reflected until after the fmr01 bit is cleared to 0. 2. in cpu rewrite mode, bits pm10 and pm13 in the pm1 regi ster are set to 1. the rewrite control program can only be executed in the internal ram or in an external ar ea that is enabled for use when the pm13 bit = 1. when the pm13 bit = 0 and the flash memory is used in 4-mbyt e mode, the extended accessible area (40000h to bffffh) cannot be used. table 22.1 flash memory version specifications item specification flash memory rewrite mode 3 modes (cpu re write, standard serial i/o, parallel i/o) erase block program rom 1 see figure 22.1 ?flash memory block diagram? program rom 2 1 block (16 kbytes) data flash 2 blocks (4 kbytes each) program method in units of 2 words erase method block erase program and erase control method program and erase controlled by software command protect method the lock bit protects each block number of commands 8 commands program and erase endurance 100 times (2, 3) data retention 10 years rom code protection parallel i/o and standard serial i/o modes are supported table 22.2 flash memory rewrite modes overview flash memory rewrite mode cpu rewrite mode (1) standard serial i/o mode parallel i/o mode function program rom 1, program rom 2, and data flash are rewritten when the cpu executes software commands. ew0 mode: rewritable in areas other than flash memory (2) ew1 mode: rewritable in the flash memory program rom 1, program rom 2, and data flash are rewritten using a dedicated serial pro- grammer. standard serial i/o mode 1: clock synchronous serial i/o standard serial i/o mode 2: clock asynchronous serial i/o program rom 1, pro- gram rom 2 and data flash are rewritten using a dedicated parallel pro- grammer. areas which can be rewritten program rom 1, program rom 2, and data flash program rom 1, program rom 2, and data flash program rom 1 and program rom 2 operating mode single-chip mode memory expansion mode (ew0 mode) boot mode parallel i/o mode rom programmer none serial programmer parallel programmer rej09b0392-0064 rev.0.64 oct 12, 2007 page 264 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.1 memory map the flash memory contains program rom 1, program rom 2, and data flash. figure 22.1 shows a flash memory block diagram. program rom 1 is divided into several blocks, each of which can be protected (locked) from program or erase. program rom 1 and program rom 2 can be rewri tten in cpu rewrite, standard serial i/o, and par- allel i/o modes. program rom 2 can be used when the prg2c0 bit in the prg2c register is set to 0 (program rom 2 enabled). the user boot code area is in program rom 2. data flash can be used when the pm10 bit in the pm1 register is set to 1 (0e000h to 0ffffh: data flash). data flash is divided into block a and block b. figure 22.1 flash memory block diagram notes: 1. to specify a block, use an even address in that block. 2. shown here is a block diagram during single-chip mode. program rom 1 0f0000h 0e0000h 0effffh 0d0000h 0dffffh 0c0000h 0cffffh 0b0000h 0bffffh 0a0000h 0affffh 0fffffh 090000h 09ffffh 080000h 08ffffh 00efffh 00e000h 00ffffh 00f000h 013fffh 010000h data flash program rom 2 block a block b block 5 : 64 kbytes block 7 : 64 kbytes block 6 : 64 kbytes block 2 : 64 kbytes block 4 : 64 kbytes block 3 : 64 kbytes block 0 : 64 kbytes block 1 : 64 kbytes rej09b0392-0064 rev.0.64 oct 12, 2007 page 265 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.1.1 boot mode the microcomputer enters boot mode when a hardware reset occurs while an ?l? signal is applied to the p5_5 pin and an ?h? signal is applied to pins cnvss and p5_0. in boot mode, user boot mode or stan- dard serial i/o mode is selected in accordance with the data in the user boot code area. refer to 22.4 ?standard serial i/o mode? for details. 22.1.2 user boot function user boot mode can be selected by the status of a port when the mcu starts in boot mode. table 22.3 shows the user boot function specifications. set ?userboot? in ascii code to the addresses 13 ff0h to 13ff7h in the user boot code area and select a port for entry from addresses13ff8h to 13ff9h and the start level with the address 13ffbh. after starting boot mode, user boot mode or standard serial i/o mode is selected in accordance with the level of the selected port. in addition, if addresses 13ff0h to 13ff7h are set to ?userboot? in ascii code and address 13ff8h to 13ffbh are set to ?00h?, user boot mode is selected. in user boot mode, the program of address 10000h (the start address of program rom2) is executed. figure 22.2 shows user boot code area, table 22.4 shows the start mode, tables 22.5 and 22.6 the values to be set to the user boot code area. figure 22.2 user boot code area table 22.3 user boot function specifications item specification entry pin none or select a port from p0_0 to p10_7 user boot start level select ?h? or ?l? user boot start address a ddress 10000h (the start address of program rom 2) user boot start address user boot code area 10000h 13ff0h 13fffh program rom 2 boot code address reserved space bit start level select 13ff0h 13ff8h 13ffah 13ffbh 13ffch 13fffh user boot code area port information for entry rej09b0392-0064 rev.0.64 oct 12, 2007 page 266 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version table 22.4 start mode (when the port pj_j is selected for entry) boot code (13ff0h to 13ff7h) port information for entry port pi_j input level start mode address (13ff8h to 13ff9h) bit (13ffah) start level select (13ffbh) ?userboot? in ascii code 0000h 00h 00h ? user boot mode pi register address 00h to 07h (value of j) 00h h standard serial i/o mode l user boot mode pi register address 00h to 07h (value of j) 01h h user boot mode l standard serial i/o mode other than ?userboot? in ascii code ? ? ? ? standard serial i/o mode i=0 to 10, j=0 to 7 notes: 1. do not use another combination of values apart from table 22.4. 2. refer to table 22.5 ??userboot?in ascii code? 3. refer to table 22.6 ?addresses of selectable ports for entry? table 22.5 ?userboot?in ascii code address 13ff0h 13ff1h 13ff2h 13ff3h 13ff4h 13ff5h 13ff6h 13ff7h ascii code 55h (u) 73h (s) 65h (e) 72h (r) 42h (b) 6fh (o) 6fh (o) 74h (t) upper- case lower-case upper- case lower-case table 22.6 addresses of selectable ports for entry port address port address p0 03e0h p6 03ech p1 03e1h p7 03edh p2 03e4h p8 03f0h p3 03e5h p9 03f1h p4 03e8h p10 03f4h p5 03e9h rej09b0392-0064 rev.0.64 oct 12, 2007 page 267 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.2 functions to pr event flash memory from rewriting the flash memory has a built-in rom code protect f unction for parallel i/o mode and a built-in id code check function for standard i/o mode to preven t the flash memory from reading or rewriting. 22.2.1 rom code protect function the rom code protect function inhibits the flash me mory from being read or rewritten during parallel input/output mode. figure 22.3 shows the ofs1 addr ess. the ofs1 address is located in block 0 in program rom 1. the rom code protect function is enabled when the romcp1 bit is set to 0. when exiting rom code protect, erase block 0 in cluding the ofs1 address by the cpu rewrite mode or the standard serial i/o mode. 22.2.2 id code check function use the id code check function in standard serial i/o mode. the id code sent from the serial program- mer is compared with the id code written in the fl ash memory for a match. if the id codes do not match, commands sent from the serial programmer are not ac cepted. however, if the four bytes of the reset vector are ?ffffffffh?, id codes are not compar ed, allowing all commands to be accepted. the id codes are 7-byte data stored consecutively, starting with the first byte, into addresses 0fffdfh, 0fffe3h, 0fffebh, 0fffefh, 0ffff3h, 0ffff7h, and 0ffffbh. the flash memory must have a program with the id codes set in these addresses. table 22.7 shows address for id code stored. the reserved character sequence of the ascii c odes ?alerase? is used for forced erase function. the reserved character sequence of the ascii codes ?protect? is used for standard serial i/o mode dis- abled function. table 22.7 lists reserved character sequence. when the id codes stored in the id code addresses in the user rom area are set to the ascii codes: ?alerase? as the combination table listed in table 22.7, forced erase function becomes active. when the forced erase function or standard serial i/o mode disabled function is not used, use another combi- nation of the ascii codes. table 22.7 reserved character sequence (reserved word) id code address reserved word combination of ld code (ascii) alerase protect fffdfh id1 41h (a) 50h (upper-case p) fffe3h id2 4ch (l) 72h (lower-case r) fffebh id3 65h (e) 6fh (lower-case o) fffefh id4 52h (r) 74h (lower-case t) ffff3h id5 41h (a) 65h (lower-case e) ffff7h id6 53h (s) 63h (lower-case c) ffffbh id7 45h (e) 74h (lower-case t) reserve word for forced erase function: a set of reserved characters that match all the id code addresses in sequence as the combination table listed in table 22.7. rej09b0392-0064 rev.0.64 oct 12, 2007 page 268 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.2.3 forced erase function this function is available only in standard serial i/o mode. when the reserved characters, ?alerase? in ascii co de, are sent from the serial programmer as id codes, the content of the user rom area will be erased at onc e. however, if the id codes stored in the id code addresses in the user rom area are set to other than a reserved word ?alerase? (other than the combination table listed in table 22.7) when the romcp bit in the romcp address is set to other than 11b (rom code protect enabled), forced erase fu nction is ignored and id code check is executed. table 22.8 lists conditions and functions for forced erase function. when both the id codes sent from the serial pr ogrammer and the id codes stored in the id code addresses correspond to the reserved word ?aler ase?, the user rom area will be erased. however, when the serial progra mmer sends other than ?alerase?, even if the id codes stored in the id code addresses are ?alerase?, there is no id match and any command is ignored. the user rom area remains protected accordingly. 22.2.4 standard serial i/ o mode disable function this function is available in standard serial i/o mode. when the id codes in the id code stored addresses are set to ?protect? in ascii code, the mcu does not communicate with a serial program- mer. therefore, the flash memory ca nnot be read, written or erased by a serial programmer. user boot mode can be selected, when the id codes set to ?protect?. when the id codes are set to ?protect? and the ro mcp1 bit in the address ofs1 is set to 0 (rom code protect enabled), rom code protection cannot be disabled by a serial programmer. therefore, the flash memory cannot be read, written or erased by a serial or parallel programmer. table 22.8 forced erase function condition function id code from serial programmer code in id code stored address romcp1 bit in the ofs1 address alerase alerase ? user rom area all erase (forced erase function) other than alerase (1) 1 (rom code protect disabled) 0 (rom code protect enabled) id code check other than alerase alerase ? id code check (no id match) other than alerase (1) ? id code check note: 1. for the combination of the stored addresses is ?protect?, refer to 22.2.4 ?standard serial i/o mode disable function? . rej09b0392-0064 rev.0.64 oct 12, 2007 page 269 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version figure 22.3 ofs1 address figure 22.4 address for id code stored optional feature select address (1) b7 1 1 1 1 1 b6 b5 b4 b1 b2 b3 symbol ofs1 address fffffh bit symbol bit name rw after reset ffh (2) b0 function notes : 1. the ofs1 address exists in flash memory. set the values when writing a program. 2. the ofs1 address is set to ffh when a block including the ofs1 address is erased. 3. set the wdton bit to 0 (watchdog timer starts automati cally after reset) when setting the csproini bit to 0 (count source protection mode enabled after reset). wdton watchdog timer start select bit (3) 0 : watchdog timer starts automatically after reset 1 : watchdog timer is in a stopped state after reset rw ? (b2-b1) rw reserved bits set to 1 romcp1 rw rom code protection bit 0 : rom code protection enabled 1 : rom code protection disabled ? (b6-b4) rw reserved bits set to 1 csproini rw after-reset count source protection mode select bit (3) 0 : count source protection mode enabled after reset 1 : count source protection mode disabled after reset reset vector nmi vector dbc vector watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 0fffffh to 0ffffch 0ffffbh to 0ffff8h 0ffff7h to 0ffff4h 0ffff3h to 0ffff0h 0fffefh to 0fffech 0fffebh to 0fffe8h 0fffe7h to 0fffe4h 0fffe3h to 0fffe0h 0fffdfh to 0fffdch 4 bytes address ofs1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 270 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3 cpu rewrite mode in cpu rewrite mode, the flash memory can be re written when the cpu executes software commands. program rom 1, program rom 2, and data flash can be rewritten with the microcomputer mounted on a board without using a rom programmer. the program and block erase commands are executed only in each block area of program rom 1, pro- gram rom 2, and data flash. erase-write 0 (ew0) mode and erase-write 1 (ew1) mo de are provided as cpu rewrite mode. table 22.9 lists differences between erase-write 0 (ew0) and erase-write 1 (ew1) modes. notes: 1. do not generate an interrupt (except nmi interrupt) or st art a dma transfer. 2. when in cpu rewrite mode, bits pm10 and pm13 in the pm1 register are set to 1. the rewrite control program can only be executed in the internal ram or in an external area that is enabled for use when the pm13 bit = 1. when the pm13 bit = 0 and the flash memory is used in 4-mbyte mode, the extended accessible area (40000h to bffffh) cannot be used. table 22.9 ew0 mode and ew1 mode item ew0 mode ew1 mode operating mode ? single-chip mode ? memory expansion mode single-chip mode rewrite control pro- gram allocatable area ? program rom 1 ? program rom 2 ? program rom 1 ? program rom 2 rewrite control pro- gram executable area the rewrite control program must be transferred to any area other than the flash memory (e.g., ram) before being executed (2) the rewrite control program can be exe- cuted in program rom 1, program rom 2, and data flash. rewritable area ? program rom 1 ? program rom 2 ? data flash program rom 1, program rom 2, and data flash, excluding blocks with the rewrite control program software command restriction none ? program and block erase commands cannot be executed in a block having the rewrite control program. ? read status register command cannot be used. mode after program or erase read status register mode read array mode cpu state during auto write and auto erase operating maintains hold state (i/o ports maintains the state before the command execu- tion) (1) flash memory sta- tus detection ? read bits fmr00, fmr06, and fmr07 in the fmr0 register by pro- gram ? execute the read status register com- mand to read bits sr7, sr5, and sr4 in the status register. read bits fmr00, fmr06, and fmr07 in the fmr0 register by program rej09b0392-0064 rev.0.64 oct 12, 2007 page 271 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.1 ew0 mode the microcomputer enters cpu rewrite mode by setting the fmr01 bit in the fmr0 register to 1 (cpu rewrite mode enabled) and is ready to accept comma nds. ew0 mode is selected by setting the fmr60 bit in the fmr6 register to 0. figure 22.7 shows setting and resetting of ew0 mode. the software commands control programming and erasin g. the fmr0 register or the status register indicates whether a program or erase oper ation is completed as expected or not. 22.3.2 ew1 mode ew1 mode is selected by setting the fmr60 bit to 1 after setting the fmr01 bit to 1. figure 22.8 shows setting and resetting of ew1 mode. the fmr0 register indicates whether or not a program or erase operation has been completed as expected. the status register cannot be read in ew1 mode. when a program / erase operation is initiated, the cpu halts all program execution until the operation is completed. 22.3.3 flash memory control register (r egisters fmr0, fmr1, fmr2 and fmr6) figures 22.5 to 22.8 show the registers fmr0, fmr1, fmr2 and fmr6, respectively. rej09b0392-0064 rev.0.64 oct 12, 2007 page 272 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version figure 22.5 fmr0 register b7 0 0 b6 b5 b4 b1 b2 b3 symbol fmr0 address 0220h after reset 00000001b b0 function bit symbol bit name rw flash memory control register 0 rw ? (b5) reserved bit set to 0 rw ? (b4) reserved bit set to 0 notes : 1. to set the fmr01 bit to 1, write a 0 and then a 1 in succession. make sure no interrupts or dma transfers will occur before writing a 1 after writing a 0. while in ew0 mode, write to this bit from a program in other than the flash memory. enter read array mode, and then set this bit to 0. 2. to set the fmr02 bit to 1, write a 0 and then a 1 in succession when the fmr01 bit = 1. make sure no interrupts or no dma transfers will occur before writing a 1 after writing a 0. 3. write to the fmstp bit from a program in area other than the flash memory. 4. bits fmr06 and fmr07 are cleared to 0 by executing the clear status command. 5. the fmstp bit is valid when the fmr01 bit = 1 (cpu rewrite mode). if the fmr01 bit = 0, although the fmstp bit can be set to 1 by writing 1 in a program, the flash memory is neither placed in low power mode nor initialized. 6. this status includes writing or reading with the lock bit program, block blank check, or read lock bit status command. 7. when the fmr23 bit in the fmr 2 register is set to 1 (low-current consumption), do not set the fmstp bit to 1 (flash memory stop). also, when the fmstp bit is set to 1, do not set the fmr23 bit to 1. rw fmr01 cpu rewrite mode select bit (1) 0 : cpu rewrite mode disabled 1 : cpu rewrite mode enabled ro fmr00 ry / by status flag 0 : busy (being written or erased) (6) 1 : ready flash memory stop bit (3, 5, 7) rw fmstp 0 : flash memory operation enabled 1 : flash memory operation stopped (placed in low power mode, flash memory initialized) rw fmr02 lock bit disable select bit (2) 0 : lock bit enabled 1 : lock bit disabled ro fmr07 erase status flag (4) 0 : terminated normally 1 : terminated in error ro fmr06 program status flag (4) 0 : terminated normally 1 : terminated in error rej09b0392-0064 rev.0.64 oct 12, 2007 page 273 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version figure 22.6 fmr1 register b7 0 b6 b5 b4 b1 b2 b3 symbol fmr1 address 0221h after reset 00x0xx0xb b0 function bit symbol bit name rw flash memory control register 1 rw fmr11 write to fmr6 register enable bit 0 : disabled 1 : enabled ro ? (b0) reserved bit read as undefined value ro ? (b3-b2) reserved bits read as undefined value rw ? (b5) no register bit. if necessary, set to 0. read as undefined value rw ? (b4) reserved bit set to 0 rw fmr17 data flash wait bit (1) 0 : 1 wait 1 : follow the setting of the pm17 bit ro fmr16 lock bit status flag 0 : lock 1 : unlock note : 1. when 2.7 v vcc1 3.0 v and f(bclk) 16 mhz, or when 3.0 v < vcc1 5.5 v and f(bclk) 20 mhz, one wait is necessary to read the data flash. use the pm17 or fmr17 bit to set one wait. rej09b0392-0064 rev.0.64 oct 12, 2007 page 274 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version figure 22.7 fmr2 register b7 0 b6 b5 b4 b1 b2 b3 symbol fmr2 address 0222h after reset xxxx0000b b0 function bit symbol bit name rw flash memory control register 2 notes: 1. slow read mode can be used when f(bclk) 5 mhz. when f(bclk) > 5 mhz, set the fmr22 bit to 0 (slow read mode disabled). 2. the low-current consumption read mode can be used when f(bclk) 32.768 khz. when f(bclk) > 32.768 khz, set the fmr23 bit to 0 (low-current consumption read mode disabled). 3. to set the fmr01 bit to 1, write a 0 and then a 1 in succession. make sure no interrupts or dma transfers will occur before writing a 1 after writing a 0. 4. this bit enables the mode to reduce the amount of current consumption when reading the flash memory. to rewrite flash memory (cpu rewrite mode), set the fmr22 and fmr23 bits to 0. 5. set the fmr23 bit to 1 (low-current consumption read mode enabled) after the fmr22 bit is set to 1 (slow read mode enabled). also, set the fmr22 bit to 0 (slow read mode disabled) after the fmr23 bit is set to 0 (slow read mode disabled). do not write the fmr22 and fmr23 bits at same time. 6. when the fmr23 bit is set to 1, do not set the fmstp bit in the fmr0 register to 1 (flash memory stopped). also, when the fmstp bit is set to 1, do not set the fmr23 bit to 1. 7. when the fmr23 bit in the fmr2 register is set to 1 (low-current consumption read mode enabled), do not enter wait mode or stop mode. to enter wait mode or stop mode, set the fmr23 bit to 0 (low- current consumption read mode disabled) before entering. rw fmr22 slow read mode enable bit (1, 3, 4) 0 : disabled 1 : enabled rw ? (b1-b0) reserved bit set to 0 rw fmr23 low-current consumption read mode enable bit (2, 3, 4, 5, 6, 7) 0 : disabled 1 : enabled ? (b7-b4) no register bit. if necessary, set to 0. read as undefined value 0 ? rej09b0392-0064 rev.0.64 oct 12, 2007 page 275 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version figure 22.8 fmr6 register b7 1 0 b6 b5 b4 b1 b2 b3 symbol fmr6 address 0230h after reset xx0xxx00b b0 function bit symbol bit name rw flash memory control register 6 note : 1. to set the fmr60 bit to 1, write 1 when both bits fmr01 and fmr11 are 1. rw ? (b1) reserved bit set to 1 rw fmr60 ew1 mode select bit (1) 0 : ew0 mode 1 : ew1 mode ro ? (b4-b2) reserved bits read as undefined value ro ? (b7-b6) rw ? (b5) reserved bit set to 0 reserved bits read as undefined value rej09b0392-0064 rev.0.64 oct 12, 2007 page 276 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.3.1 fmr00 bit this bit indicates the flash memory operating state. it is set to 0 while the program, block erase, lock bit program, read lock bit status command, or blo ck blank check command is being executed; other- wise, it is set to 1. 22.3.3.2 fmr01 bit the microcomputer can accept commands when th e fmr01 bit is set to 1 (cpu rewrite mode). 22.3.3.3 fmr02 bit the lock bit is disabled by setting the fmr02 bit to 1 (lock bit disabled). (refer to 22.3.6 ?data pro- tect function? .) the lock bit is enabled by setting the fmr02 bit to 0 (lock bit enabled). the fmr02 bit does not change the lock bit status bu t disables the lock bit function. if an erase com- mand is executed when the fmr02 bit is set to 1, the lock bit status changes 0 (locked) to 1 (unlocked) after command execution is completed. 22.3.3.4 fmstp bit the fmstp bit resets the flash memory control circuits and minimizes power consumption in the flash memory. access to the flash memory is disabl ed when the fmstp bit is set to 1 (flash memory stops). set the fmstp bit by program in an area other than the flash memory. set the fmstp bit to 1 if one of the followings occurs: ? a flash memory access error occurs while erasing or programming in ew0 mode (the fmr00 bit does not switch back to 1 (ready)). ? low-power consumption mode or on-chip oscillator low-power consumption mo de is entered use the following steps to stop the flash memory. (1) set the fmstp bit to 1 (2) wait tps (the wait time to stabilize the flash memory circuit) use the following steps to restart. (1) set the fmstp bit to 0 (2) wait tps (the wait time to st abilize the flash memory circuit) figure 22.13 shows a flow chart illustrating how to start and stop the flash memory processing before and after low-power co nsumption mode or on-chip os cillator low-power consumption mode. follow the procedure on this flow chart. when entering stop or wait mode, the flash memory is automatically turned off. when exiting stop or wait mode, the flash memory is turned back on . the fmr0 register does not need to be set. 22.3.3.5 fmr06 bit this is a read-only bit indicating an auto program ope ration state. the fmr06 bit is set to 1 when a program error occurs; otherwise, it is set to 0. refer to 22.3.8 ?full status check? . 22.3.3.6 fmr07 bit this is a read-only bit indicating the auto erase operation status. the fmr07 bit is set to 1 when an erase error occurs; otherwis e, it is set to 0. the fmr07 bit is also used for blank check. for details, refer to 22.3.8 ?full status check? . 22.3.3.7 fmr11 bit the fmr11 bit enables programming to the fmr6 register. rej09b0392-0064 rev.0.64 oct 12, 2007 page 277 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.3.8 fmr16 bit this is a read-only bit indicating the execut ion result of the read lock bit status command. when the block, where the read lock bit status comma nd is executed, is lock ed, the fmr16 bit is set to 0. when the block, where the read lock bit status command is executed, is unl ocked, the fmr16 bit is set to 1. 22.3.3.9 fmr17 bit this is a bit to select wait state for data flash. 22.3.3.10 fmr22 bit this bit enables the mode to reduce the amount of current consumption when reading the flash mem- ory. when rewriting the flash memory (cpu rewr ite mode), set the fmr22 bit to 0 (slow read mode disabled). also, when f(bclk) > 5 mhz, set the fmr22 bit to 0 (slow read mode disabled). figure 22.9 shows setting and resetting of the slow read mode. figure 22.9 setting and resetting of slow read mode after writing 0, write 1 ( enabled) to the fmr22 bit write 0 to fmr22 bit return to the prior frequency of the cpu clock setting procedure resetting procedure set the frequency of cpu clock to 5 mhz or less process in slow read mode slow read mode is completed slow read mode rej09b0392-0064 rev.0.64 oct 12, 2007 page 278 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.3.11 fmr23 bit this bit enables the mode to reduce the amount of current consumption when reading the flash mem- ory. when rewriting the flash memory (cpu rewrit e mode), set the fmr23 bit to 0 (low-current con- sumption read mode disabled). this bit is effective when the fmr22 bit is enabled. when f(bclk) > 32.768 khz, set the fmr23 bit to 0 (low-current consumption read mode disabled). figure 22.10 shows setting and resetting of the low-current consumption read mode. figure 22.10 setting and resetting of low-current consumption read mode after writing 0, write 1 (enabled) to the fmr23 bit low-current consumption read mode write 1 to the cm07 bit to select the sub clock in cpu clock (1) setting procedure set the cm05 bit to 1 (main clock oscillation stop) write 0 to fmr23 bit (2) return to the prior cpu clock slow read mode is completed resetting procedure write 0 to fmr22 bit (2) after writing 0, write 1 (enabled) to the fmr22 bit process in low-current consumption mode notes : 1. this is to use the low-power consumption mode. to use 125 khz on-chip oscillator low power consumption mode, set the 125 khz on-chip oscillator divided by 8 or 16 (refer to table 10.3 setting clock related bit and modes). 2. do not write the fmr22 bit and fmr23 bit at the same time. rej09b0392-0064 rev.0.64 oct 12, 2007 page 279 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.3.12 fmr60 bit this bit is used to select ew1 mode when the fm r01 bit is set to 1 (cpu rewrite mode enabled). figure 22.11 shows setting and resetting of ew0 mode. figure 22.12 shows setting and resetting of ew1 mode. figure 22.11 setting and resetting of ew0 mode single-chip mode or memory expansion mode set registers cm0, cm1, and pm1 (1) jump to the rewrite control program transferred to an area other than the flash memory. (in the following steps, use the rewrite control program in an area other than the flash memory) transfer the rewrite control program in cpu rewrite mode to an area other than the flash memory (4) notes : 1. in cpu rewrite mode, set the cm06 bit in the cm0 register and bits cm17 and cm16 in the cm1 register to cpu clock frequency of 10 mhz or less. set the pm17 bit in the pm1 register to 1 (with wait state). 2. set the fmr01 bit to 1 immmediately after setting it to 0. do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1. set the fmr01 bit in a space other than flash memory. 3. exit cpu rewrite mode after executing the read array command. 4. when in cpu rewrite mode, bits pm10 and pm13 in the pm1 register are set to 1. the rewrite control program can only be executed in the internal ram or in an external area that is enabled for use when the pm13 bit = 1. when the pm13 bit = 0 and the flash memory is used in 4-mbyte mode, the extended accessible area (40000h to bffffh) cannot be used. procedure to enter ew0 mode rewrite control program (4) execute the read array command (3) execute the software commands set the fmr01 bit to 0 (cpu rewrite mode disabled) jump to a desired address in the flash memory set the fmr01 bit to 0, and then 1 (cpu rewrite mode enabled). (2) set the fmr11 bit to 1 (fmr6 register write enabled), and then set the fmr6 register to 02h (ew0 mode), and then set the fmr11 bit to 0 (fmr6 register write disabled). rej09b0392-0064 rev.0.64 oct 12, 2007 page 280 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version figure 22.12 setting and resetting of ew1 mode single-chip mode (1) set registers cm0, cm1, and pm1 (2) program in the rom procedure to enter ew1 mode set the fmr01 bit to 1 (cpu rewrite mode enabled) after writing a 0. (3) set the fmr11 bit to 1 (fmr6 register rewrite enabled), and then set the fmr6 register to 03h (ew1 mode), and then set the fmr11 bit to 0 (fmr6 register rewrite disabled). execute the software commands set the fmr01 bit to 0 (cpu rewrite mode disabled) notes: 1. in ew1 mode, do not enter memory expansion. 2. in cpu rewrite mode, set the cm06 bit in the cm0 register and bits cm17 and cm16 in the cm1 register to cpu clock frequency of 10 mhz or less. set the pm17 bit in the pm1 register to 1 (with wait state). 3. to set the fmr01 bit to 1, write a 0 and then a 1 to the fmr01 bit. make sure no interrupts or no dma transfers will occur before writing a 1 after writing a 0. when setting the fmr11 bit to 1, set 1 while the fmr01 bit is set to 1. rej09b0392-0064 rev.0.64 oct 12, 2007 page 281 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version figure 22.13 processing before and after low-pow er consumption mode or on-chip oscillator low-power consumption mode jump to the low-power consumption mode or on-chip oscillator low-power consumption mode program transferred to an area other than the flash memory. (in the following steps, use the low-power consumption mode or on-chip oscillator low- power consumption mode program in an area other than the flash memory.) transfer the low-power consumption mode or on-chip oscillator low-power consumption mode program to an area other than the flash memory notes: 1. set the fmstp bit to 1 after the fmr01 bit is set to 1 (cpu rewrite mode enabled). 2. wait until clock stabilizes to switch clock source of the cpu clock to the main clock or sub clock. 3. add tps wait time by program. do not access the flash memory during this wait time. 4. before entering wait mode or stop mode, be sure to set the fmr01 bit to 0. start main clock oscillation wait until the flash memory stabilizes (tps) (3) set the fmstp bit to 1 (the flash memory stops operating. in a low-po wer consumption state) (1) switch clock source of the cpu clock. the main clock stops (2) process in low-power consumption mode or on-chip oscillator low-power consumption mode (4) set the fmstp bit to 0 (flash memory operation) set the fmr01 bit to 1 after setting to 0 (cpu rewrite mode enabled) set the fmr01 bit to 0 (cpu rewrite mode disabled) low-power consumption mode or on-chip oscillator low-power consumption mode program jump to a desired address in the flash memory wait until oscillation stabilizes switch clock source of the cpu clock (2) rej09b0392-0064 rev.0.64 oct 12, 2007 page 282 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.4 precautions on cpu rewrite mode 22.3.4.1 operating speed set the cm06 bit in the cm0 register and bits cm17 and cm16 in the cm1 register to a cpu clock frequency of 10 mhz or less before entering cpu rewrite mode (ew0 or ew1 mode). also, set the pm17 bit in the pm1 register to 1 (wait state). 22.3.4.2 prohibited instructions the following instructions cannot be used in ew 0 mode because the cpu tries to read data in the flash memory: the und instruction, into instruction, jmps instructio n, jsrs instruction, and brk instruction. 22.3.4.3 interrupts (ew0 mode) ? to use interrupts with vectors in a relocatable vector table, reloca te the vectors to the ram area. ?the nmi and watchdog timer interrupts are available since registers fmr0 and fmr1 are forcibly reset when either interrupt occurs. allocate the jump addresses for each interrupt routine to the fixed vector table. flash memory rewrite operation stops when the nmi or watchdog timer interrupt occurs. execute the rewrite program again after exiting the interrupt routine. ? the address match interrupt is not available sinc e the cpu tries to read data in the flash memory. 22.3.4.4 interrupts (ew1 mode) ? do not acknowledge any interrupts with vectors in a relocatable vector table or address match inter- rupt during the auto program or auto erase period. ? do not use the watchdog timer interrupt. ?the nmi interrupt is available since registers fmr0 and fmr1 are forcibly reset when the interrupt occurs. allocate the jump address for the interrupt routine to the fixed vector table. flash memory rewrite operation stops when the nmi interrupt occurs. execute the rewrite program again after exit- ing the interrupt routine. 22.3.4.5 how to access to set the fmr01 or fmr02 bit to 1, write a 1 after first setting the bit to 0. make sure that no inter- rupts or no dma transfers will occur before writing a 1 after writing a 0. 22.3.4.6 rewrite (ew0 mode) if the supply voltage drops while rewriting the bloc k where the rewrite control program is stored, the rewrite control program is not correctly rewritten. this may cause the flash memory not to be rewrit- ten. if this error occurs, use standard serial i/o mode or parallel i/o mode for rewriting. 22.3.4.7 rewrite (ew1 mode) do not rewrite any block in which th e rewrite control program is stored. 22.3.4.8 dma transfer in ew1 mode, do not generate a dma transfer while the fmr00 bit in the fmr0 register is set to 0 (auto programming or auto erasing). rej09b0392-0064 rev.0.64 oct 12, 2007 page 283 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.4.9 writing command and data write commands and data to even addresses. 22.3.4.10 wait mode when entering wait mode, set the fmr01 bit to 0 (c pu rewrite mode disabled) before executing the wait instruction. 22.3.4.11 stop mode to enter stop mode, set the fmr01 bit to 0 (cpu rewrite mode disabled), and then disable dma transfer before setting the cm10 bit to 1 (stop mode). 22.3.4.12 low-power consumpt ion mode and on-chip os cillator low-power con- sumption mode when the cm05 bit is set to 1 (main clock stopped), do not execute the following commands: ? program ? block erase ? lock bit program ? read lock bit status ? block blank check rej09b0392-0064 rev.0.64 oct 12, 2007 page 284 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.5 software commands software commands are described below. read and write the command code and data in 16-bit units, from and to even addresses in the program rom 1, program rom 2, and data flash. when the com- mand code is written, the 8 high-order bits (d15 to d8) are ignored. srd : data in the status register (d7 to d0) wa0 : address which low-order words are written (the address specified in the first bus cycle is the same even address as th e address specified in the second bus cycle.) wa1 : address which high-order words are written wd0 : write data low-order word (16 bits) wd1 : write data high-order word (16 bits) ba : highest-order block address (even address) x : given even address in the program rom 1, program rom 2, and data flash xx : eight high-order bits of command code (ignored) 22.3.5.1 read array command the read array command reads the flash memory. by writing the command code xxffh in the first bus cycle, read array mode is entered. content of a specified address can be read in 16-bit units by entering an address to be read after the next bus cycle. the microcomputer remains in read array mode until another command is written. therefore, con- tents from multiple addresses can be read consecutively. 22.3.5.2 read status register command the read status register comma nd reads the status register. by writing the command code xx70h in the first bus cy cle, the status register can be read in the sec- ond bus cycle (refer to 22.3.7 ?status register? l). read an even address in the program rom 1, program rom 2, and data flash. do not execute this command in ew1 mode. table 22.10 software commands command first bus cycle second bus cycle third bus cycle mode address data (d15 to d0) mode address data (d15 to d0) mode address data (d15 to d0) read array write x xxffh read status register write x xx70h read x srd clear status register write x xx50h program write wa0 xx41h write wa0 wd0 write wa1 wd1 block erase write x xx20h write ba xxd0h lock bit program write ba xx77h write ba xxd0h read lock bit status write x xx71h write ba xxd0h block blank check write x xx25h write ba xxd0h rej09b0392-0064 rev.0.64 oct 12, 2007 page 285 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.5.3 clear status register command the clear status register command clears the status register. by writing xx50h in the first bus cycle, bits fmr07 and fmr06 in the fmr0 register are set to 00b, and bits sr5 and sr4 in the status reg- ister are set to 00b. 22.3.5.4 program command the program command writes 2-word (4 bytes) data to the flash memory. by writing xx41h in the first bus cycle and data to the write address in the se cond and third bus cycles, an auto program opera- tion (data program and verify) will st art. the address value specified in the first bus cycle must be the same even address as the write address specified in the second bus cycle. the fmr00 bit in the fmr0 register indicates whether an auto program operation has been com- pleted. the fmr00 bit is set to 0 (busy) during auto program and to 1 (ready) while in an auto pro- gram operation. after the completion of an auto program operation, the fmr06 bit in the fmr0 register indicates whether or not the auto program operation has been completed as expected. (refer to 22.3.8 ?full status check? .) an address that is already written cannot be altere d or rewritten. figure 22.14 shows a flow chart of the program command programming. the lock bit protects each block from being programmed inadvertently. (refer to 22.3.6 ?data pro- tect function? .) in ew1 mode, do not execute this command on the bl ock to which the rewrite control program is allo- cated. in ew0 mode, the microcomputer enters read stat us register mode as soon as an auto program operation starts. the status register can be read. the sr 7 bit in the status register is set to 0 at the same time an auto program operation starts. it is set to 1 when the auto program operation is com- pleted. the microcomputer remains in read stat us register mode until the read array command is written. after completion of an auto program operati on, the status register indicates whether or not the auto program operation has been completed as expected. figure 22.14 program command start write the command code xx41h to an address to be written fmr00 = 1? program operation is completed no yes write data to an address to be written full status check note: 1. write the command code and data to even addresses. rej09b0392-0064 rev.0.64 oct 12, 2007 page 286 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.5.5 block erase command by writing xx20h in the first bus cycle and xxd0h in the second bu s cycle to the highest-order even address of a block, an auto eras e operation (erase and verify) w ill start in the specified block. the fmr00 bit in the fmr0 register indicates whet her an auto erase operation has been completed. the fmr00 bit is set to 0 (busy) during auto erase and to 1 (ready) when the auto erase operation is completed. after the completion of an auto erase operatio n, the fmr07 bit in the fmr0 register indicates whether or not the auto erase operation has been completed as expected. (refer to 22.3.8 ?full sta- tus check? .) figure 22.15 shows a block erase command. the lock bit protects each block from being erased inadvertently. (refer to 22.3.6 ?data protect function? .) in ew1 mode, do not execute this command on the bl ock where the rewrite c ontrol program is allo- cated. in ew0 mode, the microcomputer ente rs read status register mode as soon as an auto erase opera- tion starts. the status register can be read. the sr7 bit in the status register is set to 0 at the same time an auto erase operation starts. it is set to 1 when an auto erase operation is completed. the microcomputer remains in read status register mode until the read array command or read lock bit status command is written. if an erase error occurs, execute the clear status register command and then block erase command at least 3 time s until an erase error is not generated. figure 22.15 block erase command write the command code xx20h (1) write xxd0h to the highest- order block address block erase operation is completed yes start fmr00 = 1? no yes full status check (2, 3) notes: 1. write the command code and data to even addresses. 2. refer to figure 22.15 full status check and handling procedure for each error. 3. if an erase error occurs, execute the clear status register command and then block erase command at least 3 times until an erase error is not generated. rej09b0392-0064 rev.0.64 oct 12, 2007 page 287 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.5.6 lock bit program command the lock bit program command sets the lock bit for a specified block to 0 (locked). by writing xx77h in the first bus cycle and xxd0h in the second bu s cycle to the highest-order even address of a block, the lock bit for the specified bloc k is set to 0. the address value specified in the first bus cycle must be the same highest-order addre ss of a block specified in the second bus cycle. figure 22.16 shows a flow chart of the lock bit program command programming. execute read lock bit status command to read lock bit state (lock bit data). the fmr00 bit in the fmr0 register indicates w hether a lock bit program operation is completed. refer to 22.3.6 ?data protect function? for details on lock bit functions and how to set it to 1 (unlocked). figure 22.16 lock bit program command write the command code xx77h to the highest-order block address start note: 1. write the command code and data to even addresses. full status check lock bit program operation is completed yes fmr00 = 1? no write xxd0h to the highest- order block address rej09b0392-0064 rev.0.64 oct 12, 2007 page 288 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.5.7 read lock bit status command the read lock bit status command reads the lock bit state of a specified block. by writing xx71h in the first bus cycle and xxd0h in the second bu s cycle to the highest-order even address of a block, the fmr16 bit in the fmr1 register stores information on the lock bit status of a specified block. read the fmr16 bi t after the fmr00 bit in the fmr0 register is set to 1 (ready). figure 22.17 shows a flow chart of the read lock bit status command programming. figure 22.17 read lock bit status command block is not locked write the command code xx71h fmr16 = 0? block is locked no yes write xxd0h to the highest- order block address start fmr00 = 1? no yes note: 1. write the command code and data to even addresses. rej09b0392-0064 rev.0.64 oct 12, 2007 page 289 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.5.8 block blank check the block blank check command checks whether or not a specified block is blank (state after erase). by writing xx25h in the first bus cycle and xxd0h in the second bu s cycle to the highest-order even address of a block, the check result is stored in the fmr07 bit in the fmr0 register. read the fmr07 bit after the fmr00 bit in the fmr0 register is set to 1 (ready). the block blank check command is valid for unlocked blocks. if the block blank check command is executed to a block whose lock bi t is 0 (locked), the fmr07 bit (sr5) is set to 1 (not blank) regard- less of the fmr02 bit state. figure 22.18 shows a flow chart of th e block blank check command programming. figure 22.18 block blank check command not blank write the command code xx25h fmr07 = 1? blank no yes write xxd0h to the highest- order block address start fmr00 = 1? no yes note: 1. write the command code and data to even addresses. rej09b0392-0064 rev.0.64 oct 12, 2007 page 290 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.6 data protect function each block in the flash memory has a nonvolatile lo ck bit. the lock bit is enabled by setting the fmr02 bit to 0 (lock bit enabled). the lock bit allows each bl ock to be individually pr otected (locked) against program and erase. this prevents data from being inadvertently written to or erased from the flash memory. a block changes its status according to the lock bit status: ? when the lock bit status is set to 0, the blo ck is locked (block is protected against program and erase). ? when the lock bit status is set to 1, the block is not locked (block can be programmed or erased). the lock bit status is set to 0 (locked) by execut ing the lock bit program command and to 1 (unlocked) by erasing the block. no commands can set the lock bit status to 1. the lock bit status can be read by the read lock bit status command. when the fmr02 bit is set to 1, the lock bit functi on is disabled, and all blocks are unlocked. however, individual lock bit status remains unchanged. the lock bit function is enabled by setting the fmr02 bit to 0. lock bit status is retained. if the block erase command is executed while the fmr02 bi t is set to 1, the target block or all blocks are erased regardless of lock bit status. the lock bit status of each block is set to 1 after an erase operation is completed. refer to 22.3.5 ?software commands? for details on each command. 22.3.7 status register the status register indicates the flash memory operation state and whether or not an erase or program operation is completed as expected. bits fmr00, fmr06, and fmr07 in the fmr0 register indicate status register states. table 22.11 shows the status register. in ew0 mode, the status register ca n be read when the followings occur. ? any even address in the program rom 1, program rom 2, or data flash is read after writing the read status register command. ? any even address in the program rom 1, program rom 2, or data flash is read from when the pro- gram, block erase, lock bit program, or block blank check command is executed until when the read array command is executed. 22.3.7.1 sequence status (bits sr7 and fmr00) the sequence status indicates the flash memory operation state. it is set to 0 while the program, block erase, lock bit program, block blank check, or read lock bit status command is being executed; otherwise, it is set to 1. 22.3.7.2 erase status (bits sr5 and fmr07) refer to 22.3.8 ?full status check? . 22.3.7.3 program status (bits sr4 and fmr06) refer to 22.3.8 ?full status check? . rej09b0392-0064 rev.0.64 oct 12, 2007 page 291 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version d0 to d7 are the data buses read when the read status register command is executed. bits fmr07 (sr5) and fmr06 (sr4) are set to 0 when the clear status register command is executed. when the fmr07 (sr5) or fmr06 bit (sr4) is set to 1, the program, block erase, lock bit program, block blank check, and read lock bit status commands are not accepted. table 22.11 status register bits in status register bit in fmr0 register status name definition value after reset 01 sr0 (d0) - reserved - - - sr1 (d1) - reserved - - - sr2 (d2) - reserved - - - sr3 (d3) - reserved - - - sr4 (d4) fmr06 program status terminated normally terminated in error 0 sr5 (d5) fmr07 erase status terminated normally terminated in error 0 sr6 (d6) - reserved - - - sr7 (d7) fmr00 sequencer status busy ready 1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 292 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.3.8 full status check if an error occurs when a program or erase operat ion is completed, bits fmr06 and fmr07 in the fmr0 register are set to 1, indicating a specific er ror. therefore, execution results can be confirmed by checking these status (full status check). table 22.12 lists errors and fmr0 register state. figure 22.19 shows a full status check and han- dling procedure for each error. notes: 1. the flash memory enters read array mode by wr iting command code xxffh in the second bus cycle of the commands. the command code written in the first bus cycle becomes invalid. 2. when the fmr02 bit is set to 1 (lock bit disabled ), no error occurs even un der the conditions above. table 22.12 errors and fmr0 register state fmr00 register (status register) state error error occurr ence conditions fmr07 bit (sr5 bit) fmr06 bit (sr4 bit) 11 command sequence error ? command is written incorrectly ? a value other than xxd0h or xxffh is written in the second bus cycle of the lock bit program or block erase command (1) 1 0 erase error ? the block erase command is executed on a locked block (2) ? the block erase command is executed on an unlocked block, but auto erase operation is not completed as expected ? the block blank check command is executed, and the check result is not blank ? the block blank check command is executed on a locked block 0 1 program error ? the program command is executed on a locked block (2) ? the program command is executed on an unlocked block, but program operation is not completed as expected ? the lock bit program command is executed, but the lock bit is not written as expected (2) rej09b0392-0064 rev.0.64 oct 12, 2007 page 293 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version figure 22.19 full status check and handling procedure for each error full status check fmr06 =1 and fmr07=1? no command sequence error yes fmr07=0? yes erase error no yes program error no full status check completed (1) execute the clear status register command and set bits fmr06 and fmr07 to 0 (completed as expected) . (2) rewrite command and execute again. (1) execute the clear status register command and set the fmr07 bit to 0. (2) execute the read lock bit status command. set the fmr02 bit to 1 (lock bit disabled) if the lock bit in the block where the error occurred is set to 0 (locked). (3) execute the block erase command again. (4) execute (1), (2), and (3) at least 3 times until an erase error is not generated. note: if similar error still occurs, that block cannot be used. if the lock bit is set to 1 (unlocked) in (2) above, that block cannot be used. note: when either fmr06 or fmr07 bit is set to 1 (terminated by error), the program, block erase, lock bit program, block blank check, and read lock bit status commands cannot be accepted. execute the clear status register command before each command. fmr06=0? [when a program operation is executed] (1) execute the clear status register command and set the fmr06 bit to 0 (completed as expected) . (2) execute the read lock bit status command and set the fmr02 bit to 1 if the lock bit in the block where the error occurred is set to 0. (3) execute the program command again. note: if similar error occurs, that block cannot be used. if the lock bit is set to 1 in (2) above, that block cannot be used. [when a lock bit program operation is executed] (1) execute the clear status register command and set the fmr06 bit to 0. (2) set the fmr02 bit in the fmr0 register to 1. (3) execute the block erase command to erase the block where the error occurred. (4) execute the lock bit program command again. note: if similar error occurs, that block cannot be used. rej09b0392-0064 rev.0.64 oct 12, 2007 page 294 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.4 standard serial i/o mode in standard serial i/o mode, the serial programmer supporting the m16c/64 group can be used to rewrite the program rom 1, program rom 2, and data flash in the microcomputer mounted on a board. for more information about the serial programmer, contact your serial programmer manufacturer. refer to the user's manual included with your serial programmer for instructions. table 22.13 lists pin functions (f lash memory standard serial i/o mode). figures 22.20 and 22.21 show pin connections in serial i/o mode. 22.4.1 id code check function the id code check function determines whether t he id codes sent from the serial programmer match those written in the flash memory. (refer to 22.2 ?functions to prevent flash memory from rewrit- ing? .) rej09b0392-0064 rev.0.64 oct 12, 2007 page 295 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version notes: 1. when using the standard serial i/o mode, the inte rnal pull-up is enabled for the txd1 (p6_7) pin while the reset pin is ?l?. 2. when using the standard serial i/o mode, pins p 0_0 to p0_7 and p1_0 to p1_7 may become indeter- minate while the p8_4 pin is ?h? and the reset pin is ?l?. if this causes a program, apply ?l? to the p8_4 pin. table 22.13 pin functions (flash memory standard serial i/o mode) pin name i/o power supply description vcc1, vcc2, vss power input - apply the flash program and erase voltage to the vcc1 pin, and vcc2 to the vcc2 pin. the vcc apply condition is that vcc2 = vcc1. apply 0 v to the vss pin. cnvss cnvss i vcc1 connect to vcc1 pin. reset reset input i vcc1 reset input pin. while the reset pin is ?l? level, input a 20- cycle or longer clock to the xin pin. xin clock input i vcc1 connect a ceramic resonator or crystal oscillator between pins xin and xout. to input an externally generated clock, input it to the xin pin and open the xout pin. xout clock output o vcc1 byte byte input i vcc1 connect this pin to vcc1 or vss. avcc, avss analog power sup- ply input connect avss to vss and avcc to vcc1, respectively. vref reference voltage input i reference voltage input pin for a/d converter. connect to vcc1. p0_0 to p0_7 input port p0 i vcc2 input ?h? or ?l? level signal or open. p1_0 to p1_7 input port p1 i vcc2 input ?h? or ?l? level signal or open. p2_0 to p2_7 input port p2 i vcc2 input ?h? or ?l? level signal or open. p3_0 to p3_7 input port p3 i vcc2 input ?h? or ?l? level signal or open. p4_0 to p4_7 input port p4 i vcc2 input ?h? or ?l? level signal or open. p5_1 to p5_4, p5_6, p5_7 input port p5 i vcc2 input ?h? or ?l? level signal or open. p5_0 ce input i vcc2 input ?h? level signal. p5_5 epm input i vcc2 input ?l? level signal. p6_0 to p6_3 input port p6 i vcc1 input ?h? or ?l? level signal or open. p6_4 / rts1 busy output o vcc1 standard serial i/o mode 1: busy signal output pin standard serial i/o mode 2: monitor signal output pin to check the boot program operation p6_5/clk1 sclk input i vcc1 standard serial i/o mode 1: serial clock input pin standard serial i/o mode 2: input ?l?. p6_6 / rxd1 rxd input i vcc1 serial data input pin. p6_7 / txd1 txd input o vcc1 serial data output pin. (1) p7_0 to p7_7 input port p7 i vcc1 input ?h? or ?l? level signal or open. p8_0 to p8_3, p8_6, p8_7 input port p8 i vcc1 input ?h? or ?l? level signal or open. p8_4 p8_4 input i vcc1 input ?l? level signal. (2) p8_5 / nmi nmi input i vcc1 input ?h? or ?l? level signal or open. p9_0 to p9_7 input port p9 i vcc1 input ?h? or ?l? level signal or open. p10_0 to p10_7 input port p10 i vcc1 input ?h? or ?l? level signal or open. rej09b0392-0064 rev.0.64 oct 12, 2007 page 296 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version figure 22.20 pin connections for standard serial i/o mode (1) vss rxd txd sclk connect oscillator circuit cnvss ce epm busy reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 vcc2 vcc1 m16c / 64 group flash memory version package: prqp0100jd-b (100p6f-a) signal value cnvss vcc1 epm vss reset vss to vcc1 ce vcc2 mode setup method rej09b0392-0064 rev.0.64 oct 12, 2007 page 297 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version figure 22.21 pin connections for standard serial i/o mode (2) cnvss reset vss ce connect oscillator circuit busy epm sclk rxd txd 1 2345678910111213141516171819202122232425 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 vcc2 vcc1 m16c / 64 group flash memory version package: plqp0100kb-a (100p6q-a) signal value cnvss vcc1 epm vss reset vss to vcc1 ce vcc2 mode setup method rej09b0392-0064 rev.0.64 oct 12, 2007 page 298 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.4.2 example of circuit applicati on in the standard serial i/o mode figures 22.22 and 22.23 show examples of circuit application in standard serial i/o mode 1 and mode 2, respectively. refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer. figure 22.22 circuit application in standard serial i/o mode 1 cnvss sclk input busy output reset input microcomputer p5_0 (ce) p5_5 (epm) reset user reset signal txd output rxd input notes: 1. control pins and external circuitry will vary according to a programmer. for more information, see the programmer manual. 2. in this example, modes are switched between single-chip mode and standard serial input / output mode by controlling the cnvss input with a switch. 3. if in standard serial input / output mode 1 there is a possibility that the user reset signal will go low during serial input / output mode, break the connection between the user reset signal and reset pin by using, for example, a jumper switch. p6_5 / clk1 p6_7 / txd1 p6_6 / rxd1 p6_4 / rts1 vcc1 vcc2 vcc1 vcc1 vcc1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 299 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version figure 22.23 circuit application in standard serial i/o mode 2 cnvss monitor output txd output microcomputer p5_0 (ce) p5_5 (epm) rxd intput p6_4 / rts1 p6_5 / clk1 p6_7 / txd1 p6_6 / rxd1 note: 1. in this example, modes are switched between single-chip mode and standard serial input / output mode by controlling the cnvss input with a switch. reset input reset user reset signal vcc1 vcc1 vcc2 rej09b0392-0064 rev.0.64 oct 12, 2007 page 300 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 22. flash memory version 22.5 parallel i/o mode in parallel i/o mode, the program rom 1 and program rom 2 can be rewritten by a parallel programmer supporting the m16c/64 group. contact your parallel programmer manufacturer for more information on the parallel programmer. refer to the user's manual included with your parallel programmer for instruc- tions. 22.5.1 rom code protect function the rom code protect function prevents the flash memory from being read and rewritten. (refer to 22.2 ?functions to prevent flash memory from rewriting? .) rej09b0392-0064 rev.0.64 oct 12, 2007 page 301 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics 23. electrical characteristics 23.1 electrical characteristics table 23.1 absolute maximum ratings symbol parameter condition rated value unit vcc1, vcc2 supply voltage vcc1=vcc2 =avcc ? 0.3 to 6.5 v avcc analog supply voltage vcc1=avcc ? 0.3 to 6.5 v vi input voltage reset , cnvss, byte, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1, xin ? 0.3 to vcc1+0.3 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, ? 0.3 to vcc2+0.3 v p7_0, p7_1, p8_5 ? 0.3 to 6.5 v vo output voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, xout ? 0.3 to vcc1+0.3 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 ? 0.3 to vcc2+0.3 v p7_0, p7_1, p8_5 ? 0.3 to 6.5 v pd power dissipation ? 40 c rej09b0392-0064 rev.0.64 oct 12, 2007 page 303 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics notes: 1. referenced to vcc1=avcc=vref=3.0 to 5.5v, vss=avss=0v at topr = -20 to 85 c / -40 to 85 c unless otherwise speci- fied. 2. set ad frequency as follows: when vcc1 = 4.0 to 5.5 v, 2 mhz ad 25 mhz when vcc1 = 3.2 to 4.0 v, 2 mhz ad 16 mhz when vcc1 = 3.0 to 3.2 v, 2 mhz ad 10 mhz 3. use when vref=vcc1. table 23.3 a/d conversion characteristics (1) symbol parameter measuring condition standard unit min. typ. max. - resolution vref=vcc1 10 bits inl integral non-linearity error 10bit vref= vcc1= 5.0v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input 3 lsb vref= vcc1= 3.3v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input 3 lsb vref= vcc1= 3.0v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input 3 lsb - absolute accuracy 10bit vref= vcc1= 5.0v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input 3 lsb vref= vcc1 =3.3v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input 3 lsb vref= vcc1 =3.0v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input 3 lsb - tolerance level impedance 3 k dnl differential non-linearity error 1 lsb -offset error 3 lsb - gain error 3 lsb rladder ladder resistance vref=vcc1 10 40 k tconv 10-bit conversion time vref=vcc1=5v, ad=25mhz 1.60 s tsamp sampling time 0.60 s vref reference voltage vcc1 v via analog input voltage 0 vref v rej09b0392-0064 rev.0.64 oct 12, 2007 page 304 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics notes: 1. referenced to vcc1=vref=3.3 to 5.5v, vss=avss=0v at topr = -20 to 85 c / -40 to 85 c unless otherwise specified. 2. this applies when using one d/a converter, with the d/a register for the unused d/a converter set to ?00h?. the resistor ladd er of the a/d converter is not included. also, when d/a register c ontents are not ?00h?, the ivref will flow even if vref id disco n- nected by the a/d control register. notes: 1. referenced to vcc1=2.7 to 5.5v at topr = 0 to 60 c unless otherwise specified. 2. definition of program and erase endurance the program and erase endurance refers to the number of per-block erasures. if the program and erase endurance is n (n=100), each block can be erased n times. for example, if a 4 kbyte block is erased after writing two word data 1,024 times, each to a different address, this counts as one program and erase endur ance. data cannot be written to the same address more than once with- out erasing the block. (rewrite prohibited) 3. topr = -40 to 85 c / -20 to 85 c table 23.4 d/a conversion characteristics (1) symbol parameter measuring condition standard unit min. typ. max. - resolution 8bits - absolute accuracy 2.5 lsb tsu setup time 3 s ro output resistance 6k ivref reference power supply input current (note 2) 1.5 ma table 23.5 flash memory version electrical characteristics (1) symbol parameter standard unit min. typ. max. - program and erase endurance (2) other than data flash 100 cycle data flash 100 cycle - 2 word program time (vcc1=3.3v at topr=25 c) other than data flash 150 s data flash 300 s - lock bit program time (vcc1=3.3v at topr=25 c) other than data flash 70 s data flash 140 s - block erase time (vcc1=3.3v at topr=25 c) 4-kbyte block 0.20 s - 16-kbyte block 0.20 s - 64-kbyte block 0.20 s tps flash memory circuit stabilization wait time 50 s - data hold time (3) 10 year table 23.6 flash memory version program / erase voltage and read operation voltage characteristics (at topr = 0 to 60 c) flash program, erase voltage flash read operation voltage vcc2 = 2.7 to 5.5 v vcc1=2.7 to 5.5 v rej09b0392-0064 rev.0.64 oct 12, 2007 page 305 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics notes: 1. vdet2 > vdet0. 2. vdet0r > vdet0 is not guaranteed. 3. the voltage detection circuit is designed to use when vcc1 is set to 5v. note: 1. when vcc1 = 5v. table 23.7 low voltage detection ci rcuit electrical characteristics symbol parameter measuring condition standard unit min. typ. max. vdet2 low voltage detection voltage (1) vcc1=0.8v to 5.5v 3.3 3.8 4.4 v vdet0 reset level detection voltage (1) 1.9 v vdet2 -vdet0 electric potential difference of low voltage detection and reset level detection 0.3 v vdet0s low voltage reset retention voltage 0.8 v vdet0r low voltage reset release voltage (2) 2.0 v table 23.8 power supply circ uit timing characteristics symbol parameter measuring condition standard unit min. typ. max. td(p-r) time for internal power supply stabiliza- tion during powering-on vcc1=2.7v to 5.5v 5 ms td(r-s) stop release time 150 s td(w-s) low power dissipation mode wait mode release time 150 s td(s-r) brown-out detection reset (hardware reset 2) release wait time vcc1=vdet3r to 5.5v 6 (1) 20 ms td(e-a) low voltage detection circuit operation start time vcc1=2.7v to 5.5v 20 s rej09b0392-0064 rev.0.64 oct 12, 2007 page 306 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.1 power supply circuit timing diagram t d(p-r) v cc1 cpu clock t d(p-r) time for internal power supply stabilization during powering-on interrupt for (a) stop mode release or (b) wait mode release cpu clock t d(r-s) (a) (b) t d(w-s) t d(r-s) stop release time t d(w-s) low power dissipation mode wait mode release time t d(s-r) v det3r v cc1 cpu clock t d(s-r) low voltage detection reset (hardware reset 2) release wait time vc26, vc27 t d(e-a) t d(e-a) low voltage detection circuit operation start time stop operate recommended operation voltage low voltage detection circuit rej09b0392-0064 rev.0.64 oct 12, 2007 page 307 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=5v notes: 1. referenced to vcc1=vcc2=4.2 to 5.5v, vss = 0v at topr = ? 20 to 85 c / ? 40 to 85 c, f(bclk)=25mhz unless otherwise specified. table 23.9 electrical characteristics (1) (1) symbol parameter measuring condition standard unit min. typ. max. voh high output voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 ioh= ? 5ma vcc1 ? 2.0 vcc1 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 ioh= ? 5ma vcc2 ? 2.0 vcc2 voh high output voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 oh= ? 200 a vcc1 ? 0.3 vcc1 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 ioh= ? 200 a vcc2 ? 0.3 vcc2 voh high output voltage xout highpower ioh= ? 1ma vcc1 ? 2.0 vcc1 v lowpower ioh= ? 0.5ma vcc1 ? 2.0 vcc1 high output voltage xcout h ighpower with no load applied 2.9 v lowpower with no load applied 2.2 vol low output voltage p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7 iol=5ma 2.0 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 iol=5ma 2.0 vol low output voltage p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7 iol=200 a0.45v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 iol=200 a 0.45 vol low output voltage xout highpower iol=1ma 2.0 v lowpower iol=0.5ma 2.0 low output voltage xcout highpower with no load applied 0 v lowpower with no load applied 0 vt+-vt- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int7 , nmi , adtrg , cts0 to cts2 , cts5 to cts7, scl0 to scl2, scl5 to scl7, sda0 to sda2, sda5 to sda7, clk0 to clk7, ta0out to ta4out, ki0 to ki3 , rxd0 to rxd2, rxd5 to rxd7, sin3, sin4 0.2 1.0 v vt+-vt- hysteresis reset 0.2 2.5 v iih high input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte vi=5v 5.0 a iil low input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte vi=0v ? 5.0 a rpullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 vi=0v 30 50 170 k rfxin feedback resistance xin 1.5 m rfxcin feedback resistance xcin 15 m vram ram retention voltage at stop mode 2.0 v rej09b0392-0064 rev.0.64 oct 12, 2007 page 308 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics notes: 1. referenced to vcc1=vcc2=4.2 to 5.5v, vss = 0v at topr = ? 20 to 85 c / ? 40 to 85 c, f(bclk)=25mhz unless otherwise specified. 2. with one timer operated using fc32. 3. this indicates the memory in which the program to be executed exists. 4. idet is dissipation current when the following bit is set to ?1? (detection circuit enabled). idet2: vc27 bit in the vcr2 register idet0: vc25 bit in the vcr2 register table 23.10 electrical characteristics (2) (1) symbol parameter measuring condition standard unit min. typ. max. icc power supply current (vcc1=vcc2=4.0v to 5.5v) in single-chip mode, the output pins are open and other pins are vss flash memory f(bclk)=25mhz, no division, pll operation 20 ma no division, 125 khz on-chip oscillation 450 a flash memory program f(bclk)=10mhz, vcc1=5.0v 20 ma flash memory erase f(bclk)=10mhz, vcc1=5.0v 30 ma flash memory f(bclk)=32khz low power dissipation mode, ram (3) 45 a f(bclk)=32khz low power dissipation mode, flash memory (3) fmr22=fmr23=1 160 a 125 khz on-chip oscillation, wait mode 12 a f(bclk)=32khz wait mode (2) , oscillation capability high 11.5 a f(bclk)=32khz wait mode (2) , oscillation capability low 6.2 a stop mode to p r = 2 5 c 3.0 a idet2 low voltage detection dissipation current (4) 3.0 a idet0 reset area detection dissipation current (4) 6.0 a rej09b0392-0064 rev.0.64 oct 12, 2007 page 309 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=5v timing requirements (vcc1 = vcc2 = 5v, vss = 0v, at topr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) note: 1. the condition is vcc1=vcc2=3.0 to 5.0v. notes: 1. calculated according to t he bclk frequency as follows: 2. calculated according to t he bclk frequency as follows: n is ?2? for 1-wait setting, ?3? for 2-wait setting and ?4? for 3-wait setting. 3. calculated according to t he bclk frequency as follows: n is ?2? for 2-wait setting, ?3? for 3-wait setting. table 23.11 external cloc k input (xin input) (1) symbol parameter standard unit min. max. tc external clock input cycle time 50 ns tw(h) external clock input high pulse width 25 ns tw(l) external clock input low pulse width 25 ns tr external clock rise time 15 ns tf external clock fall time 15 ns table 23.12 memory expansion mode and microprocessor mode symbol parameter standard unit min. max. tac1(rd-db) data input access time (for setting with no wait) (note 1) ns tac2(rd-db) data input access time (for setting with wait) (note 2) ns tac3(rd-db) data input access time (when accessing multiplex bus area) (note 3) ns tsu(db-rd) data input setup time 40 ns tsu(rdy-bclk) rdy input setup time 30 ns tsu(hold- bclk) hold input setup time 40 ns th(rd-db) data input hold time 0 ns th(bclk-rdy) rdy input hold time 0 ns th(bclk-hold) hold input hold time 0 ns 0.5x10 9 fbclk () ----------------------- -45ns [] ? n0.5 ? () x 10 9 fbclk () ------------------------------------ -45ns [] ? n0.5 ? () x 10 9 fbclk () ------------------------------------ -45ns [] ? rej09b0392-0064 rev.0.64 oct 12, 2007 page 310 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=5v timing requirements (vcc1 = vcc2 = 5v, vss = 0v, at topr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 23.13 timer a input (counter input in event counter mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 100 ns tw(tah) taiin input high pulse width 40 ns tw(tal) taiin input low pulse width 40 ns table 23.14 timer a input (gating input in timer mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 400 ns tw(tah) taiin input high pulse width 200 ns tw(tal) taiin input low pulse width 200 ns table 23.15 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 200 ns tw(tah) taiin input high pulse width 100 ns tw(tal) taiin input low pulse width 100 ns table 23.16 timer a input (external trigge r input in pulse width modulation mode) symbol parameter standard unit min. max. tw(tah) taiin input high pulse width 100 ns tw(tal) taiin input low pulse width 100 ns table 23.17 timer a input (counter incremen t/decrement input in event counter mode) symbol parameter standard unit min. max. tc(up) taiout input cycle time 2000 ns tw(uph) taiout input high pulse width 1000 ns tw(upl) taiout input low pulse width 1000 ns tsu(up-tin) taiout input setup time 400 ns th(tin-up) taiout input hold time 400 ns table 23.18 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 800 ns tsu(tain-taout) taiout input setup time 200 ns tsu(taout-tain) taiin input setup time 200 ns rej09b0392-0064 rev.0.64 oct 12, 2007 page 311 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=5v timing requirements (vcc1 = vcc2 = 5v, vss = 0v, at topr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 23.19 timer b input (counte r input in event counter mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time (counted on one edge) 100 ns tw(tbh) tbiin input high pulse width (counted on one edge) 40 ns tw(tbl) tbiin input low pulse width (counted on one edge) 40 ns tc(tb) tbiin input cycle time (counted on both edges) 200 ns tw(tbh) tbiin input high pulse width (counted on both edges) 80 ns tw(tbl) tbiin input low pulse width (counted on both edges) 80 ns table 23.20 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high pulse width 200 ns tw(tbl) tbiin input low pulse width 200 ns table 23.21 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high pulse width 200 ns tw(tbl) tbiin input low pulse width 200 ns table 23.22 a/d trigger input symbol parameter standard unit min. max. tc(ad) adtrg input cycle time 1000 ns tw(adl) adtrg input low pulse width 125 ns table 23.23 serial interface symbol parameter standard unit min. max. tc(ck) clki input cycle time 200 ns tw(ckh) clki input high pulse width 100 ns tw(ckl) clki input low pulse width 100 ns td(c-q) txdi output delay time 80 ns th(c-q) txdi hold time 0 ns tsu(d-c) rxdi input setup time 70 ns th(c-d) rxdi input hold time 90 ns table 23.24 external interrupt inti input symbol parameter standard unit min. max. tw(inh) inti input high pulse width 250 ns tw(inl) inti input low pulse width 250 ns rej09b0392-0064 rev.0.64 oct 12, 2007 page 312 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=5v switching characteristics (vcc1 = vcc2 = 5v, vss = 0v, at topr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: f(bclk) is 12.5mhz or less. 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr x ln (1 ? vol / vcc2) by a circuit of the right figure. for example, when vol = 0.2vcc2, c = 30pf, r = 1k , hold time of output ?l? level is t = ? 30pf x 1k x in(1 ? 0.2vcc2 / vcc2) = 6.7ns. figure 23.2 ports p0 to p14 measurement circuit table 23.25 memory expansion and micropro cessor modes (for setting with no wait) symbol parameter measuring condition standard unit min. max. td(bclk-ad) address output delay time see figure 23.2 25 ns th(bclk-ad) address output hold time (in relation to bclk) 4 ns th(rd-ad) address output hold time (in relation to rd) 0 ns th(wr-ad) address output hold time (in relation to wr) (note 2) ns td(bclk-cs) chip select output delay time 25 ns th(bclk-cs) chip select output hold time (in relation to bclk) 4 ns td(bclk-ale) ale signal output delay time 15 ns th(bclk-ale) ale signal output hold time ? 4ns td(bclk-rd) rd signal output delay time 25 ns th(bclk-rd) rd signal output hold time 0 ns td(bclk-wr) wr signal output delay time 25 ns th(bclk-wr) wr signal output hold time 0 ns td(bclk-db) data output delay time (in relation to bclk) 40 ns th(bclk-db) data output hold time (in relation to bclk) (3) 4ns td(db-wr) data output delay time (in relation to wr) (note 1) ns th(wr-db) data output hold time (in relation to wr) (3) (note 2) ns td(bclk-hlda) hlda output delay time 40 ns 0.5x10 9 fbclk () ----------------------- -40ns [] ? 0.5x10 9 fbclk () ----------------------- -10ns [] ? dbi r c p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf p11 p12 p13 p14 rej09b0392-0064 rev.0.64 oct 12, 2007 page 313 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=5v switching characteristics (vcc1 = vcc2 = 5v, vss = 0v, at topr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull- up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr x ln (1 ? vol / vcc2) by a circuit of the right figure. for example, when vol = 0.2vcc2, c = 30pf, r = 1k , hold time of output ?l? level is t = ? 30pf x 1k x in(1 ? 0.2vcc2 / vcc2) = 6.7ns. table 23.26 memory expansion and microprocessor modes (for 1- to 3-wait setting and external area access) symbol parameter measuring condition standard unit min. max. td(bclk-ad) address output delay time see figure 23.2 25 ns th(bclk-ad) address output hold time (in relation to bclk) 4 ns th(rd-ad) address output hold time (in relation to rd) 0 ns th(wr-ad) address output hold time (in relation to wr) (note 2) ns td(bclk-cs) chip select output delay time 25 ns th(bclk-cs) chip select output hold time (in relation to bclk) 4 ns td(bclk-ale) ale signal output delay time 15 ns th(bclk-ale) ale signal output hold time -4 ns td(bclk-rd) rd signal output delay time 25 ns th(bclk-rd) rd signal output hold time 0 ns td(bclk-wr) wr signal output delay time 25 ns th(bclk-wr) wr signal output hold time 0 ns td(bclk-db) data output delay time (in relation to bclk) 40 ns th(bclk-db) data output hold time (in relation to bclk) (3) 4ns td(db-wr) data output delay time (in relation to wr) (note 1) ns th(wr-db) data output hold time (in relation to wr) (3) (note 2) ns td(bclk-hlda) hlda output delay time 40 ns n0.5 ? () x10 9 fbclk () ------------------------------------ 4 0 n s [] ? 0.5x10 9 fbclk () ----------------------- -10ns [] ? dbi r c n is ?1? for 1-wait setting, ?2? for 2-wait setting and ?3? for 3-wait setting. (bclk) is 12.5mhz or less. rej09b0392-0064 rev.0.64 oct 12, 2007 page 314 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=5v switching characteristics (vcc1 = vcc2 = 5v, vss = 0v, at topr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to t he bclk frequency as follows: 2. calculated according to t he bclk frequency as follows: n is ?2? for 2-wait sett ing, ?3? for 3-wait setting. 3. calculated according to t he bclk frequency as follows: 4. calculated according to t he bclk frequency as follows: table 23.27 memory expansion and microprocessor modes (for 2- to 3-wait setting, external area access and multiplex bus selection) symbol parameter measuring condition standard unit min. max. td(bclk-ad) address output delay time see figure 23.2 25 ns th(bclk-ad) address output hold time (in relation to bclk) 4 ns th(rd-ad) address output hold ti me (in relation to rd) (note 1) ns th(wr-ad) address output hold time (in relation to wr) (note 1) ns td(bclk-cs) chip select output delay time 25 ns th(bclk-cs) chip select output hold time (in relation to bclk) 4 ns th(rd-cs) chip select ou tput hold time (in relation to rd) (note 1) ns th(wr-cs) chip select output hold time (in relation to wr) (note 1) ns td(bclk-rd) rd signal output delay time 25 ns th(bclk-rd) rd signal output hold time 0 ns td(bclk-wr) wr signal output delay time 25 ns th(bclk-wr) wr signal output hold time 0 ns td(bclk-db) data output delay time (in relation to bclk) 40 ns th(bclk-db) data output hold time (in relation to bclk) 4 ns td(db-wr) data output delay time (in relation to wr) (note 2) ns th(wr-db) data output hold time (in relation to wr) (note 1) ns td(bclk-hlda) hlda output delay time 40 ns td(bclk-ale) ale signal output delay time (in relation to bclk) 15 ns th(bclk-ale) ale signal output hold time (in relation to bclk) ? 4ns td(ad-ale) ale signal outp ut delay time (in relati on to address) (note 3) ns th(ad-ale) ale signal outp ut hold time (in relation to address) (note 4) ns td(ad-rd) rd signal output dela y from the end of address 0 ns td(ad-wr) wr signal output dela y from the end of address 0 ns tdz(rd-ad) address output floating start time 8 ns 0.5x10 9 fbclk () ----------------------- -10ns [] ? n0.5 ? () x10 9 fbclk () ------------------------------------ 4 0 n s [] ? 0.5x10 9 fbclk () ----------------------- -25ns [] ? 0.5x10 9 fbclk () ----------------------- -15ns [] ? rej09b0392-0064 rev.0.64 oct 12, 2007 page 315 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.3 timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c v cc1 =v cc2 =5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 316 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.4 timing diagram (2) t su(d-c) clk i txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) int i input t d(c-q) t h(c-d) t h(c-q) v cc1 =v cc2 =5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 317 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.5 timing diagram (3) memory expansion mo de, microprocessor mode ( effective for setting with wait ) bclk hold input hlda input measuring conditions : v cc1 =v cc2 =5v input timing voltage : determined with v il =1.0v, v ih =4.0v output timing voltage : determined with v ol =2.5v, v oh =2.5v p0, p1, p2, p3, p4, p5_0 to p5_2 (1) ( common to setting with wait and setting without wait ) notes: 1. these pins are set to high-impedance regardless of the input level of the byte pin, pm06 bit in pm0 register and pm11 bit in pm1 register. t h(bclk ? hold) t su(hold ? bclk) t d(bclk ? hlda) t d(bclk ? hlda) hi ? z rdy input t su(rdy ? bclk) t h(bclk ? rdy) rd bclk (separate bus) (multiplexed bus) wr, wrl, wrh rd (separate bus) wr, wrl, wrh (multiplexed bus) v cc1 =v cc2 =5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 318 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.6 timing diagram (4) bclk csi t d(bclk-cs) 25ns.max adi 25ns.max ale 25ns.max -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe t cyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 40ns.min t ac1(rd-db) memory expansion mode, microprocessor mode ( for setting with no wait ) measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v wr, wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 t cyc -40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 t cyc -45)ns.max t cyc = 1 f(bclk) (0.5 t cyc -10)ns.min (0.5 t cyc -10)ns.min v cc1 =v cc2 =5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 319 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.7 timing diagram (5) bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t su(db-rd) 40ns.min t h(rd-db) 0ns.min t cyc bhe read timing wr, wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 t cyc -40)ns.min (0.5 t cyc -10)ns.min t h(wr-db) dbi write timing t d(bclk-ale) t d(bclk-rd) t d(bclk-wr) 0ns.min t h(rd-ad) t ac2(rd-db) hi-z memory expansion mode, microprocessor mode ( for 1-wait setting and external area access ) ? measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v (1.5 t cyc -45)ns.max t cyc = f(bclk) 1 (0.5 tcyc-10)ns.min v cc1 =v cc2 =5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 320 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.8 timing diagram (6) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 2-wait setting and external area access ) bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max hi-z t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc hi-z t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 25ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (1.5 t cyc -40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 t cyc -10)ns.min measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v t ac2(rd-db) (2.5 t cyc -45)ns.max tcyc = 1 f(bclk) v cc1 =v cc2 =5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 321 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.9 timing diagram (7) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 3-wait setting and external area access ) bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max hi-z t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 25ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (2.5 t cyc -40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 t cyc -10)ns.min measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v t ac2(rd-db) (3.5 t cyc -45)ns.max t cyc = 1 f(bclk) t cyc v cc1 =v cc2 =5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 322 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.10 timing diagram (8) memory expansion mode, microprocessor mode ( for 1- or 2-wait setting, external area access and multiplex bus selection ) bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale t h(bclk-ale) ? 4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(rd-cs) t h(rd-ad) bhe adi /dbi t h(rd-db) 0ns.min t d(ad-ale) read timing t d(bclk-wr) 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) ? 4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) t h(wr-db) adi /dbi data output wr,wrl, wrh write timing address (0.5 t cyc -10)ns.min address data input 40ns.min (0.5 t cyc -10)ns.min t d(bclk-ale) t d(bclk-rd) (0.5 t cyc -10)ns.min t h(wr-cs) address t d(ad-ale) (0.5 t cyc -25)ns.min (1.5 t cyc -40)ns.min (0.5 t cyc -10)ns.min t d(bclk-ale) (0.5 t cyc -25)ns.min address 25ns.max t su(db-rd) t ac3(rd-db) (0.5 t cyc -10)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t d(ad-wr) 0ns.min measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v t h(ale-ad) (1.5 t cyc -45)ns.max (0.5 t cyc -15)ns.min v cc1 =v cc2 =5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 323 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.11 timing diagram (9) read timing write timing memory expansion mode, microprocessor mode ( for 3-wait setting, external area access and multiplex bus selection ) bclk csi ale rd adi /dbi adi bhe (no multiplex) bclk csi ale adi /dbi t cyc t d(bclk-ad) 25ns.max t cyc data output t h(bclk-cs) 4ns.min t d(bclk-cs) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max t h(bclk-rd) 0ns.min t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(rd-ad) (0.5 t cyc -10)ns.min t h(bclk-ad) 4ns.min t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t h(bclk-db) 4ns.min t h(bclk-wr) 0ns.min t h(wr-ad) (0.5 t cyc -10)ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t d(bclk-ale) 25ns.max t d(bclk-wr) 25ns.max t h(wr-db) (0.5 t cyc -10)ns.min data input address address adi bhe (no multiplex) wr, wrl wrh measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v t d(ad-ale) (0.5 t cyc -25)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t ac3(rd-db) t d(bclk-db) 40ns.max (0.5 t cyc -10)ns.min t h(wr-cs) t d(db-wr) (2.5 tcyc-40)ns.min t d(ad-wr) 0ns.min t h(rd-cs) (0.5 t cyc -10)ns.min t d(ad-ale) (0.5 t cyc -25)ns.min t h(ale-ad) (2.5 t cyc -45)ns.max t cyc = 1 f(bclk) (0.5 tcyc-15)ns.min t h(bclk-ale) -4ns.min v cc1 =v cc2 =5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 324 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=3v notes: 1. referenced to vcc1 = vcc2 = 2.7 to 3.3v, vss = 0v at topr = ? 20 to 85 c / ? 40 to 85 c, f(xin)=25mhz unless otherwise specified. 2. vcc1 for the port p6 to p10 and vcc2 for the port p0 to p5. table 23.28 electrical characteristics (1) (1) symbol parameter measuring condition standard unit min. typ. max. voh high out- put voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 ioh= ? 1ma vcc1 ? 0.5 vcc1 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 ioh= ? 1ma (2) vcc2 ? 0.5 vcc2 voh high output voltage xout highpower ioh= ? 0.1ma vcc1 ? 0.5 vcc1 v lowpower ioh= ? 50 avcc1 ? 0.5 vcc1 high output voltage xcout highpower with no load applied 2.9 v lowpower with no load applied 2.2 vol low out- put voltage p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7 iol=1ma 0.5 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 iol=1ma (2) 0.5 vol low output voltage xout highpower iol=0.1ma 0.5 v lowpower iol=50 a0.5 low output voltage xcout h ighpower with no load applied 0 v lowpower with no load applied 0 vt+-vt- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int7 , nmi , adtrg , cts0 to cts2 , cts5 to cts7 , scl0 to scl2, scl5 to scl7, sda0 to sda2, sda5 to sda7, clk0 to clk7, ta0out to ta4out, ki0 to ki3 , rxd0 to rxd2, rxd5 to rxd7, sin3, sin4 0.2 0.8 v vt+-vt- hysteresis reset 0.2 (0.7) 1.8 v iih high input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte vi=3v 4.0 a iil low input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte vi=0v ? 4.0 a rpul- lup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 vi=0v 50 100 500 k rfxin feedback resistance xin 3.0 m rfxcin feedback resistance xcin 25 m vram ram retention voltage at stop mode 2.0 v rej09b0392-0064 rev.0.64 oct 12, 2007 page 325 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics notes: 1. referenced to vcc1=vcc2=2.7 to 3.3v, vss = 0v at topr = ? 20 to 85 c / ? 40 to 85 c, f(bclk)=25mhz unless otherwise specified. 2. with one timer operated using fc32. 3. this indicates the memory in which the program to be executed exists. 4. idet is dissipation current when the following bit is set to ?1? (detec tion circuit enabled). idet2: vc27 bit in the vcr2 register idet0: vc25 bit in the vcr2 register table 23.29 electrical characteristics (2) (1) symbol parameter measuri ng condition standard unit min. typ. max. icc power supply current (vcc1=vcc2=2.7v to 3.6v) in single-chip mode, the output pins are open and other pins are vss flash memory f(bclk)=25mhz, no division 20 ma no division, 125 khz on-chip oscilla- tion 450 a flash memory program f(bclk)=10mhz, vcc1=3.0v 20 ma flash memory erase f(bclk)=10mhz, vcc1=3.0v 30 ma flash memory f(bclk)=32khz low power dissipation mode, ram (3) 40 a f(bclk)=32khz low power dissipation mode, flash memory (3) fmr22=fmr23=1 160 a 125 khz on-chip oscillation, wait mode 9 a f(bclk)=32khz wait mode (2) , oscillation capability high 9.5 a f(bclk)=32khz wait mode (2) , oscillation capability low 5.7 a stop mode topr =25 c 3 a idet2 low voltage detection dissipation current (4) 3 a idet0 reset area detection dissipation current (4) 6 a rej09b0392-0064 rev.0.64 oct 12, 2007 page 326 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=3v timing requirements (vcc1 = vcc2 = 3v, vss = 0v, at topr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) note: 1. the condition is vcc1=vcc2=2.7 to 3.0v. notes: 1. calculated according to t he bclk frequency as follows: 2. calculated according to t he bclk frequency as follows: n is ?2? for 1-wait setting, ?3? fo r 2-wait setting and ?4? for 3-wait setting. 3. calculated according to t he bclk frequency as follows: n is ?2? for 2-wait setting, ?3? for 3-wait setting. table 23.30 external cl ock input (xin input) (1) symbol parameter standard unit min. max. tc external clock input cycle time 50 ns tw(h) external clock input high pulse width 20 ns tw(l) external clock input low pulse width 20 ns tr external clock rise time 9 ns tf external clock fall time 9 ns table 23.31 memory expansion mode and microprocessor mode symbol parameter standard unit min. max. tac1(rd-db) data input access time (for setting with no wait) (note 1) ns tac2(rd-db) data input access time (for setting with wait) (note 2) ns tac3(rd-db) data input access time (when accessing multiplex bus area) (note 3) ns tsu(db-rd) data input setup time 50 ns tsu(rdy-bclk) rdy input setup time 40 ns tsu(hold-bclk) hold input setup time 50 ns th(rd-db) data input hold time 0 ns th(bclk-rdy) rdy input hold time 0 ns th(bclk-hold) hold input hold time 0 ns 0.5x10 9 fbclk () ----------------------- -60ns [] ? n0.5 ? () x10 9 fbclk () ------------------------------------ 6 0 n s [] ? n0.5 ? () x10 9 fbclk () ------------------------------------ 6 0 n s [] ? rej09b0392-0064 rev.0.64 oct 12, 2007 page 327 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=3v timing requirements (vcc1 = vcc2 = 3v, vss = 0v, at topr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 23.32 timer a input (counter input in event counter mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 150 ns tw(tah) taiin input high pulse width 60 ns tw(tal) taiin input low pulse width 60 ns table 23.33 timer a input (g ating input in timer mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 600 ns tw(tah) taiin input high pulse width 300 ns tw(tal) taiin input low pulse width 300 ns table 23.34 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 300 ns tw(tah) taiin input high pulse width 150 ns tw(tal) taiin input low pulse width 150 ns table 23.35 timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min. max. tw(tah) taiin input high pulse width 150 ns tw(tal) taiin input low pulse width 150 ns table 23.36 timer a input (counter increment/decrement input in event counter mode) symbol parameter standard unit min. max. tc(up) taiout input cycle time 3000 ns tw(uph) taiout input high pulse width 1500 ns tw(upl) taiout input low pulse width 1500 ns tsu(up-tin) taiout input setup time 600 ns th(tin-up) taiout input hold time 600 ns table 23.37 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 2 s tsu(tain-taout) taiout input setup time 500 ns tsu(taout-tain) taiin input setup time 500 ns rej09b0392-0064 rev.0.64 oct 12, 2007 page 328 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=3v timing requirements (vcc1 = vcc2 = 3v, vss = 0v, at topr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 23.38 timer b input (counter input in event counter mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time (counted on one edge) 150 ns tw(tbh) tbiin input high pulse width (counted on one edge) 60 ns tw(tbl) tbiin input low pulse width (counted on one edge) 60 ns tc(tb) tbiin input cycle time (counted on both edges) 300 ns tw(tbh) tbiin input hi gh pulse width (counted on both edges) 120 ns tw(tbl) tbiin input low pulse width (counted on both edges) 120 ns table 23.39 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 600 ns tw(tbh) tbiin input hi gh pulse width 300 ns tw(tbl) tbiin input low pulse width 300 ns table 23.40 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 600 ns tw(tbh) tbiin input hi gh pulse width 300 ns tw(tbl) tbiin input low pulse width 300 ns table 23.41 a/d trigger input symbol parameter standard unit min. max. tc(ad) adtrg input cycle time 1500 ns tw(adl) adtrg input low pulse width 200 ns table 23.42 serial interface symbol parameter standard unit min. max. tc(ck) clki input cycle time 300 ns tw(ckh) clki input high pulse width 150 ns tw(ckl) clki input low pulse width 150 ns td(c-q) txdi output delay time 160 ns th(c-q) txdi hold time 0ns tsu(d-c) rxdi input setup time 100 ns th(c-d) rxdi input hold time 90 ns table 23.43 external interrupt inti input symbol parameter standard unit min. max. tw(inh) inti input high pulse width 380 ns tw(inl) inti input low pulse width 380 ns rej09b0392-0064 rev.0.64 oct 12, 2007 page 329 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=3v switching characteristics (vcc1 = vcc2 = 3v, vss = 0v, at topr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: f (bclk) is 12.5mhz or less. 2. calculated according to the bclk frequency as follows: this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull- down) resistance value. hold time of data bus is expressed in t= ? cr x ln (1 ? vol / vcc2) by a circuit of the right figure. for example, when vol = 0.2vcc2, c = 30pf, r = 1k , hold time of output ?l? level is t = ? 30pf x 1k x in(1 ? 0.2vcc2 / vcc2) = 6.7ns. figure 23.12 ports p0 to p14 measurement circuit table 23.44 memory expansion and microprocessor modes (for setting with no wait) symbol parameter measuring condition standard unit min. max. td(bclk-ad) address output delay time see figure 23.12 30 ns th(bclk-ad) address output hold time (in relation to bclk) 4 ns th(rd-ad) address output hold time (in relation to rd) 0 ns th(wr-ad) address output hold time (in relation to wr) (note 2) ns td(bclk-cs) chip select output delay time 30 ns th(bclk-cs) chip select output hold time (in relation to bclk) 4 ns td(bclk-ale) ale signal output delay time 25 ns th(bclk-ale) ale signal output hold time ? 4ns td(bclk-rd) rd signal output delay time 30 ns th(bclk-rd) rd signal output hold time 0 ns td(bclk-wr) wr signal output delay time 30 ns th(bclk-wr) wr signal output hold time 0 ns td(bclk-db) data output delay time (in relation to bclk) 40 ns th(bclk-db) data output hold time (in relation to bclk) (3) 4ns td(db-wr) data output delay time (in relation to wr) (note 1) ns th(wr-db) data output hold time (in relation to wr) (3) (note 2) ns td(bclk-hlda) hlda output delay time 40 ns 0.5x10 9 fbclk () ----------------------- -40ns [] ? 0.5x10 9 fbclk () ----------------------- -10ns [] ? dbi r c p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf p11 p12 p13 p14 rej09b0392-0064 rev.0.64 oct 12, 2007 page 330 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=3v switching characteristics (vcc1 = vcc2 = 5v, vss = 0v, at topr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to t he bclk frequency as follows: 2. calculated according to t he bclk frequency as follows: 3. this standard value shows the timing when the out- put is off, and does not show hold time of data bus. hold time of data bus va ries with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t= ? cr x ln (1 ? vol / vcc2) by a circuit of the right figure. for example, when vol = 0.2vcc2, c = 30pf, r = 1k , hold time of output ?l? level is t = ? 30pf x 1k x in(1 ? 0.2vcc2 / vcc2) = 6.7ns. table 23.45 memory expansion and microprocessor modes (for 1- to 3-wait setting and external area access) symbol parameter measuring condition standard unit min. max. td(bclk-ad) address output delay time see figure 23.12 30 ns th(bclk-ad) address output hold time (in relation to bclk) 4 ns th(rd-ad) address output hold time (in relation to rd) 0 ns th(wr-ad) address output hold time (in relation to wr) (note 2) ns td(bclk-cs) chip select output delay time 30 ns th(bclk-cs) chip select output hold time (in relation to bclk) 4 ns td(bclk-ale) ale signal output delay time 25 ns th(bclk-ale) ale signal output hold time -4 ns td(bclk-rd) rd signal output delay time 30 ns th(bclk-rd) rd signal output hold time 0 ns td(bclk-wr) wr signal output delay time 30 ns th(bclk-wr) wr signal output hold time 0 ns td(bclk-db) data output delay time (in relation to bclk) 40 ns th(bclk-db) data output hold time (in relation to bclk) (3) 4ns td(db-wr) data output delay time (in relation to wr) (note 1) ns th(wr-db) data output hold time (in relation to wr) (3) (note 2) ns td(bclk-hlda) hlda output delay time 40 ns n0.5 ? () x10 9 fbclk () ------------------------------------ 4 0 n s [] ? 0.5x10 9 fbclk () ----------------------- -10ns [] ? dbi r c n is ?1? for 1-wait setting, ?2? for 2-wait setting and ?3? for 3-wait setting. (bclk) is 12.5mhz or less. rej09b0392-0064 rev.0.64 oct 12, 2007 page 331 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics vcc1=vcc2=3v switching characteristics (vcc1 = vcc2 = 5v, vss = 0v, at topr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to t he bclk frequency as follows: 2. calculated according to t he bclk frequency as follows: n is ?2? for 2-wait se tting, ?3? for 3-wait setting. 3. calculated according to t he bclk frequency as follows: 4. calculated according to t he bclk frequency as follows: table 23.46 memory expansion and microprocessor modes (for 2- to 3-wait setting, external area access and multiplex bus selection) symbol parameter measuring condition standard unit min. max. td(bclk-ad) address output delay time see figure 23.12 50 ns th(bclk-ad) address output hold time (in relation to bclk) 4 ns th(rd-ad) address output hold ti me (in relation to rd) (note 1) ns th(wr-ad) address output hold time (in relation to wr) (note 1) ns td(bclk-cs) chip select output delay time 50 ns th(bclk-cs) chip select output hold time (in relation to bclk) 4 ns th(rd-cs) chip select ou tput hold time (in relation to rd) (note 1) ns th(wr-cs) chip select output hold time (in relation to wr) (note 1) ns td(bclk-rd) rd signal output delay time 40 ns th(bclk-rd) rd signal output hold time 0 ns td(bclk-wr) wr signal output delay time 40 ns th(bclk-wr) wr signal output hold time 0 ns td(bclk-db) data output delay time (in relation to bclk) 50 ns th(bclk-db) data output hold time (in relation to bclk) 4 ns td(db-wr) data output delay time (in relation to wr) (note 2) ns th(wr-db) data output hold time (in relation to wr) (note 1) ns td(bclk-hlda) hlda output delay time 40 ns td(bclk-ale) ale signal output delay time (in relation to bclk) 25 ns th(bclk-ale) ale signal output hold time (in relation to bclk) ? 4ns td(ad-ale) ale signal outp ut delay time (in relati on to address) (note 3) ns th(ad-ale) ale signal outp ut hold time (in relation to address) (note 4) ns td(ad-rd) rd signal output dela y from the end of address 0 ns td(ad-wr) wr signal output dela y from the end of address 0 ns tdz(rd-ad) address output floating start time 8 ns 0.5x10 9 fbclk () ----------------------- -10ns [] ? 0.5x10 9 fbclk () ----------------------- - 50 ns [] ? 0.5x10 9 fbclk () ----------------------- - 40 ns [] ? 0.5x10 9 fbclk () ----------------------- -15ns [] ? rej09b0392-0064 rev.0.64 oct 12, 2007 page 332 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.13 timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c v cc1 =v cc2 =3v rej09b0392-0064 rev.0.64 oct 12, 2007 page 333 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.14 timing diagram (2) t su(d-c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) inti input t d(c-q) t h(c-d) t h(c-q) v cc1 =v cc2 =3v rej09b0392-0064 rev.0.64 oct 12, 2007 page 334 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.15 timing diagram (3) memory expansion mode, microprocessor mode (effective for setting with wait) bclk hold input hlda output measuring conditions : v cc1 =v cc2 =3v input timing voltage : determined with v il =0.6v, v ih =2.4v output timing voltage : determined with v ol =1.5v, v oh =1.5v p0, p1, p2, p3, p4, p5_0 to p5_2 (1) (common to setting with wait and setting without wait) notes: 1. these pins are set to high-impedance regardless of the input level of the byte pin, pm06 bit in pm0 register and pm11 bit in pm1 register. t h(bclk ? hold) t su(hold ? bclk) t d(bclk ? hlda) t d(bclk ? hlda) hi ? z rdy input t su(rdy ? bclk) t h(bclk ? rdy) rd bclk (separate bus) (multiplexed bus) wr, wrl, wrh rd (separate bus) wr, wrl, wrh (multiplexed bus) v cc1 =v cc2 =3v rej09b0392-0064 rev.0.64 oct 12, 2007 page 335 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.16 timing diagram (4) bclk csi t d(bclk-cs) 30ns.max adi 30ns.max ale 30ns.max -4ns.min rd 30ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe t cyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 50ns.min t ac1(rd-db) memory expansion mode, microprocessor mode ( for setting with no wait ) measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v wr, wrl, wrh 30ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 30ns.max adi t d(bclk-ad) 30ns.max ale 30ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 t cyc -40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 t cyc -60)ns.max t cyc = 1 f(bclk) (0.5 t cyc -10)ns.min (0.5 t cyc -10)ns.min v cc1 =v cc2 =3v rej09b0392-0064 rev.0.64 oct 12, 2007 page 336 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.17 timing diagram (5) bclk csi t d(bclk ? cs) 30ns.max adi t d(bclk ? ad) 30ns.max ale 30ns.max t h(bclk ? ale) ? 4ns.min rd 30ns.max t h(bclk ? rd) 0ns.min t h(bclk ? ad) 4ns.min t h(bclk ? cs) 4ns.min hi ? z dbi t su(db ? rd) 50ns.min t h(rd ? db) 0ns.min t cyc bhe read timing wr,wrl, wrh 30ns.max t h(bclk ? wr) 0ns.min bclk csi t d(bclk ? cs) 30ns.max adi t d(bclk ? ad) 30ns.max ale 30ns.max t d(bclk ? ale) t h(bclk ? ale) ? 4ns.min t h(bclk ? ad) 4ns.min t h(bclk ? cs) 4ns.min t cyc t h(wr ? ad) bhe t d(bclk ? db) 40ns.max 4ns.min t h(bclk ? db) t d(db ? wr) (0.5 t cyc ? 40)ns.min (0.5 t cyc ? 10)ns.min t h(wr ? db) dbi write timing t d(bclk ? ale) t d(bclk ? rd) (0.5 t cyc ? 10)ns.min t d(bclk ? wr) 0ns.min t h(rd ? ad) t ac2(rd ? db) hi ? z memory expansion mode, microprocessor mode ( for 1-wait setting and external area access ) (1.5 t cyc ? 60)ns.max t cyc = 1 f(bclk) v cc1 =v cc2 =3v measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 337 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.18 timing diagram (6) memory expansion mode, microprocessor mode ( for 2-wait setting, external area access and multiplex bus selection ) bclk csi t d(bclk-cs) 40ns.max adi t d(bclk-ad) 40ns.max ale t h(bclk-ale) -4ns.min rd 40ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(rd-cs) t h(rd-ad) bhe adi /dbi t h(rd-db) 0ns.min t d(ad-ale) read timing t d(bclk-wr) 40ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 40ns.max adi t d(bclk-ad) 40ns.max ale 40ns.max t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 50ns.max 4ns.min t h(bclk-db) t d(db-wr) t h(wr-db) adi /dbi data output wr,wrl, wrh write timing address (0.5 t cyc -10)ns.min address data input 50ns.min (0.5 t cyc -10)ns.min t d(bclk-ale) t d(bclk-rd) (0.5 t cyc -10)ns.min t h(wr-cs) address t d(ad-ale) (0.5 t cyc -40)ns.min (1.5 t cyc -50)ns.min (0.5 t cyc -10)ns.min t d(bclk-ale) (0.5 t cyc -40)ns.min address 40ns.max t su(db-rd) t ac3(rd-db) (0.5 t cyc -10)ns.min t h(ale-ad) t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t d(ad-wr) 0ns.min (1.5 t cyc -60)ns.max t cyc = 1 f(bclk) (0.5 t cyc -15)ns.min v cc1 =v cc2 =3v measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 338 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.19 timing diagram (7) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 3-wait setting and external area access ) bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 30ns.max hi-z t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc hi-z t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 30ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 t cyc -10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (2.5 t cyc -40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 tcyc-10)ns.min t ac2(rd-db) (3.5 t cyc -60)ns.max t cyc = 1 f(bclk) v cc1 = v cc2 = 3v measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 339 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.20 timing diagram (8) memory expansion mode, microprocessor mode ( for 2-wait setting, external area access and multiplex bus selection ) bclk csi t d(bclk-cs) 40ns.max adi t d(bclk-ad) 40ns.max ale t h(bclk-ale) -4ns.min rd 40ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(rd-cs) t h(rd-ad) bhe adi /dbi t h(rd-db) 0ns.min t d(ad-ale) read timing t d(bclk-wr) 40ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 40ns.max adi t d(bclk-ad) 40ns.max ale 40ns.max t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 50ns.max 4ns.min t h(bclk-db) t d(db-wr) t h(wr-db) adi /dbi data output wr,wrl, wrh write timing address (0.5 t cyc -10)ns.min address data input 50ns.min (0.5 t cyc -10)ns.min t d(bclk-ale) t d(bclk-rd) (0.5 t cyc -10)ns.min t h(wr-cs) address t d(ad-ale) (0.5 t cyc -40)ns.min (1.5 t cyc -50)ns.min (0.5 t cyc -10)ns.min t d(bclk-ale) (0.5 t cyc -40)ns.min address 40ns.max t su(db-rd) t ac3(rd-db) (0.5 t cyc -10)ns.min t h(ale-ad) t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t d(ad-wr) 0ns.min (1.5 t cyc -60)ns.max t cyc = 1 f(bclk) (0.5 t cyc -15)ns.min v cc1 =v cc2 =3v measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 340 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 23. electrical characteristics figure 23.21 timing diagram (9) read timing write timing memory expansion mode, microprocessor mode ( for 3-wait setting, external area access and multiplex bus selection ) bclk csi ale rd adi /dbi adi bhe (no multiplex) bclk csi ale adi /dbi t cyc t d(bclk-ad) 40ns.max t cyc data output t h(bclk-cs) 6ns.min t d(bclk-cs) 40ns.max t d(bclk-ale) 40ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 40ns.max t h(bclk-rd) 0ns.min t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(rd-ad) (0.5 t cyc -10)ns.min t h(bclk-ad) 4ns.min t d(bclk-cs) 40ns.max t d(bclk-ad) 40ns.max t h(bclk-db) 4ns.min t h(bclk-wr) 0ns.min t h(wr-ad) (0.5 t cyc -10)ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t d(bclk-ale) 40ns.max t d(bclk-wr) 40ns.max t h(wr-db) (0.5 t cyc -10)ns.min data input address address adi bhe (no multiplex) wr, wrl wrh t h(ale-ad) t d(ad-ale) (0.5 t cyc -40)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t ac3(rd-db) t d(bclk-db) 50ns.max (0.5 t cyc -10)ns.min t h(wr-cs) t d(db-wr) (2.5 t cyc -50)ns.min t d(ad-wr) 0ns.min t h(rd-cs) (0.5 t cyc -10)ns.min t d(ad-ale) (0.5 t cyc -40)ns.min (2.5 t cyc -60)ns.max t cyc = 1 f(bclk) t h(bclk-ale) -4ns.min (0.5 t cyc -15)ns.min v cc1 =v cc2 =3v measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v rej09b0392-0064 rev.0.64 oct 12, 2007 page 341 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24. precautions 24.1 sfr 24.1.1 register settings table 24.1 lists registers with write-only bits. set these registers with immediate values. when estab- lishing a next value by altering the existing value, wr ite the existing value to the ram as well as to the register. transfer the next value to the register after making changes in the ram. table 24.1 registers with write-only bits register symbol address watchdog timer reset register wdtr 037dh watchdog timer start register wdts 037eh timer a1-1 register ta11 0303h to 0302h timer a2-1 register ta21 0305h to 0304h timer a4-1 register ta41 0307h to 0306h dead time timer dtt 030ch timer b2 interrupt generation frequency set counter ictb2 030dh si/o3 bit rate register s3brg 0273h si/o4 bit rate register s4brg 0277h uart0 bit rate register u0brg 0249h uart1 bit rate register u1brg 0259h uart2 bit rate register u2brg 0269h uart5 bit rate register u5brg 0289h uart6 bit rate register u6brg 0299h uart7 bit rate register u7brg 02a9h uart0 transmit buffer register u0tb 024bh to 024ah uart1 transmit buffer register u1tb 025bh to 025ah uart2 transmit buffer register u2tb 026bh to 026ah uart5 transmit buffer register u5tb 028bh to 028ah uart6 transmit buffer register u6tb 029bh to 029ah uart7 transmit buffer register u7tb 02abh to 02aah timer a0 register ta0 0327h to 0326h timer a1 register ta1 0329h to 0328h timer a2 register ta2 032bh to 032ah timer a3 register ta3 032dh to 032ch timer a4 register ta4 032fh to 032eh rej09b0392-0064 rev.0.64 oct 12, 2007 page 342 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.2 reset 24.2.1 vcc1 when supplying power to the microcomputer, the pow er supply voltage applied to the vcc1 pin must meet the conditions of svcc. figure 24.1 timing of sv cc 24.2.2 cnvss to start to operate in si ngle-chip mode after reset, connect to vss via resistor . the internal pull-up of the cnvss pin is on immediately after hardware reset 1 or 2 is released in single-chip mode. there- fore, the cnvss pin level becomes high for two cycles of foco-s maximum. symbol parameter standard unit min. typ. max. sv cc power supply rising gradient (v cc1 ) (voltage range 0 to 2) 0.05 v / ms sv cc 2v 0v sv cc power supply rising gradient (v cc1 ) time voltage rej09b0392-0064 rev.0.64 oct 12, 2007 page 343 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.3 bus ? when hardware reset 1 or brown-ou t reset is performed with ?h? inpu t on the cnvss pin, contents of internal rom cannot be read. rej09b0392-0064 rev.0.64 oct 12, 2007 page 344 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.4 pll frequency synthesizer to use the pll frequency synthesizer, stabilize supply voltage so that the standard of the power supply ripple is met. figure 24.2 voltage fluctuation timing v p-p (ripple) f (ripple) power supply ripple allowable frequency (vcc1) vp-p (ripple) power supply ripple allowable amplitude voltage f (ripple) v cc1 symbol parameter standard unit min. typ. max. f (ripple) power supply ripple allowable frequency (v cc1 )10khz v p-p (ripple) power supply ripple allowable amplitude voltage (v cc1 = 5v) 0.5 v (v cc1 = 3v) 0.3 v v cc (| v / t|) power supply ripple rising / falling gradient (v cc1 = 5v) 0.3 v / ms (v cc1 = 3v) 0.3 v / ms rej09b0392-0064 rev.0.64 oct 12, 2007 page 345 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.5 power control ? when exiting stop mode by hardware reset 1, set the reset pin to ?l? until a main clock oscillation is stabilized. ? set the mr0 bit in the taimr register (i = 0 to 4) to 0 (pulse is not output) to use the timer a to exit stop mode. ? after the wait instruction, inse rt at least four nop instructions. when entering wait mode, the instruction queue reads ahead the instructions following wait, and depending on timing, some of these may execute before the microcomputer enters wait mode. program example when entering wait mode is shown below. program example: fset i ; wait ;enter wait mode nop ;more than four nop instructions nop nop nop ? when entering stop mode, insert a jmp.b instructio n immediately after execut ing an instruction which sets the cm10 bit in the cm1 register to 1, and then insert at least four nop instructions. when entering stop mode, the instruction queue reads ahead the instructions following the instruction which sets the cm10 bit to 1 (all clock stop), and some of these may execute before the microcomputer enters stop mode or before the interrupt routine for returning from stop mode. program example when entering stop mode program example: fset i bset 0, cm1 ; enter stop mode jmp.b l2 ; insert a jmp.b instruction l2: nop ; more than four nop instructions nop nop nop ? the clkout pin outputs high in stop mode. ther efore, when the clkout pin changes state from high to low and is immediately driven in stop mode, the low level width becomes short. ? wait until the main clock oscillati on stabilizes, before switching the clock source for the cpu clock to the main clock. similarly, wait until the sub clock oscillates stably be fore switching the clock source for the cpu clock to the sub clock. ? do not stop the externally-generated clock when the externally-generated clock is input to the xin pin and the main clock is used as the clock source for the cpu clock. stop mode clkout rej09b0392-0064 rev.0.64 oct 12, 2007 page 346 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions ? suggestions to reduce power consumption refer to the following descriptions wh en designing a system or programming. ports the processor retains the state of each i/o port even when it goes to wait mode or to stop mode. a cur- rent flows in active output ports. a pass current flows to input ports in high-impedance state. when entering wait mode or stop mo de, set non-used ports to in put and stabilize the potential. a/d converter when a/d conversion is not performed, set the adstby bit in the adcon1 register to 0 (a/d operation stop). when a/d conversion is performed, start the a/d conversion at least 1 ad cycle or longer after setting the adstby bit to 1 (a/d operation enabled). d/a converter when not performing d/a conversion, set the daie bit (i = 0, 1) in the dacon register to 0 (output inhibited) and the dai register to 00h. stopping peripheral functions use the cm02 bit in the cm0 register to stop the unnecessary peripheral functions during wait mode. switching the oscillation-driving capacity set the driving capacity to ?l ? when oscillation is stable. rej09b0392-0064 rev.0.64 oct 12, 2007 page 347 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.6 protect set the prc2 bit to 1 (write enabled) and then writ e to given sfr address, and the prc2 bit will be cleared to 0 (write protected). change the registers prot ected by the prc2 bit in the next instruction after setting the prc2 bit to 1. make sure no interrupts or dma transfers will occu r between the instruction in which the prc2 bit is set to 1 and the next instruction. rej09b0392-0064 rev.0.64 oct 12, 2007 page 348 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.7 interrupt 24.7.1 reading address 00000h do not read the address 00000h in a program. when a maskable interrupt request is accepted, the cpu reads interrupt information (interrupt number and interrupt request priority level) from the address 00000h during the interrupt sequence. at this time, th e ir bit for the accepted interrupt is cleared to 0. if the address 00000h is read in a program, the ir bit for the interrupt which has the highest priority among the enabled interrupts is cleared to 0. this factors a problem that the interrupt is canceled, or an unexpected interrupt request is generated. 24.7.2 sp setting set any value in the sp (usp, isp) before accept ing an interrupt. the sp (usp, isp) is cleared to 0000h after reset. therefore, if an interrupt is acc epted before setting any value in the sp (usp, isp), the program may go out of control. especially when using the nmi interrupt, set a value in the isp at the beginning of the program. only for the first instruction after reset, all interrupts including the nmi interrupt are disabled. 24.7.3 nmi interrupt ? the nmi interrupt cannot be disabled. if this interrupt is not used, set the pm24 bit in the pm2 reg- ister to 0 (port p8_5 function). ? stop mode cannot be entered into while input on the nmi pin is low because the cm10 bit in the cm1 register is fixed to 0. ? do not enter wait mode while input on the nmi pin is low because the cpu clock remains active even though the cpu stops, and therefore, the cu rrent consumption in the chip does not drop. in this case, normal condition is restor ed by a subsequent interrupt generated. ? set the low and high level durations of the input signal to the nmi pin to 2 cpu clock cycles + 300 ns or more. rej09b0392-0064 rev.0.64 oct 12, 2007 page 349 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.7.4 changing an inte rrupt generate factor if the interrupt generate factor is changed, the ir bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 (interrupt r equested). to use an interrupt, change the interrupt generate factor, and then be sure to clear the ir bit for that interrupt to 0 (interrupt not requested). changing the interrupt generate factor referred to here means any act of changing the source, polarity or timing of the interrupt assigned to each software interrupt number. therefore, if a mode change of any peripheral function involves changing the source, po larity or timing of an interrupt, be sure to clear the ir bit for that interrupt to 0 (interrupt not requested) after making such changes. refer to the description of each peripheral function for details about the interrupts from peripheral functions. figure 24.3 shows the procedure for changing the interrupt generate factor. figure 24.3 procedure for changing the interrupt generate factor 24.7.5 int interrupt ? either an ?l? level of at least tw (inl) width or an ?h? level of at least tw (inh) width is necessary for the signal input to pins int0 through int7 regardless of the cpu operation clock. ? if the pol bit in registers int0ic to int7ic, bits ifsr7 to ifsr0 in the ifsr register, or bits ifsr31 and ifsr30 in the ifsr3a register are ch anged, the ir bit may inadvertently set to 1 (interrupt requested). be sure to clear the ir bit to 0 (interrupt not requested) after changing any of those register bits. ir bit: a bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed notes : 1. the above settings must be executed individually. do not execute two or more settings simultaneously (using one instruction). 2. use the i flag for the inti interrupt (i = 0 to 5). for the interrupts from peripheral functions other than the inti interrupt, turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt generate factor. in this case, if the maskable interrupts can all be disabled without causing a problem, use the i flag. otherwise, use the corresponding bits ilvl2 to ilvl0 for the interrupt whose interrupt generate factor is to be changed. 3. refer to 23.7.6 rewrite the interrupt control register for details about the instructions to use and the notes to be taken for instruction execution. use the mov instruction to clear the ir bit to 0 (interrupt not requested) (3) disable interrupts (2, 3) change the interrupt generate factor (including a mode change of peripheral function) enable interrupts (2, 3) change the interrupt source change is completed rej09b0392-0064 rev.0.64 oct 12, 2007 page 350 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.7.6 rewriting the inte rrupt control register (a) the interrupt control register for any interrupt shou ld be modified in places where no requests for that interrupt may occur. otherwise, disable the interrupt before rewriting the interrupt control register. (b) to rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used. ? changing any bit other than the ir bit when interrupts corresponding to the register occur, the ir bit may not become 1 (interrupt requested) and the interrupts may be ignored. if this causes any troubles, use any of the following instructions to change registers. instruction: and, or, bclr, or bset. ? changing the ir bit depending on the instruction used, the ir bit may not always be cleared to 0 (interrupt not requested). therefore, be sure to use the mov instruction to clear the ir bit. (c) when using the i flag to disable an interrupt, set the i flag while referring to the sample program fragments shown below. (refer to (b) for details about rewriting the interrupt control registers in the sample program fragments.) examples 1 through 3 show how to prevent the i flag from being set to 1 (interrupt enabled) before the interrupt control register is rewritten, owing to t he effects of the internal bus and the instruction queue buffer. example 1: using the nop instruction to keep the program waiting until the interrupt control register is modified int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00h. nop ; nop fset i ; enable interrupts. the number of the nop instructions is as follows. pm20 = 1 (1 wait) : 2, pm20 = 0 (2 waits) : 3, when using the hold function : 4. example 2: using the dummy read to keep the fset instruction waiting int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00h. mov.w mem, r0 ; dummy read . fset i ; enable interrupts. example 3: using the popc instruction to change the i flag int_switch3: pushc flg fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00h. popc flg ; enable interrupts. rej09b0392-0064 rev.0.64 oct 12, 2007 page 351 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.7.7 watchdog timer interrupt initialize the watchdog timer after th e watchdog timer in terrupt occurs. rej09b0392-0064 rev.0.64 oct 12, 2007 page 352 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.8 dmac 24.8.1 write to the dmae bit in the dmicon re gister (i = 0 to 3) when both of the conditions below are met, follow the steps below. conditions ? the dmae bit is set to 1 (dmai is in active state) again while it remains 1. ? a dma request may occur simultaneously when the dmae bit is being written. steps (1) write a 1 to the dmae bit and dmas bit in the dmicon register simultaneously (1). (2) make sure that the dm ai is in initial state (2) in a program. if the dmai is not in initial state, repeat the above steps. note: 1. the dmas bit remains unchanged even if a 1 is writt en. however, if a 0 is wr itten to this bit, it is set to 0 (dma not requested). in order to prevent the dmas bit from being modified to 0, 1 should be written to the dmas bit when 1 is written to the dmae bit. in this way the state of the dmas bit immediately before being written can be maintained. 2. similarly, when writing to the dmae bit with a re ad-modify-write instruction, 1 should be written to the dmas bit in order to maintain a dma request which is generated during execution. 3. read the tcri register to verify whether the dmai is in initial state. if th e read value is equal to a value which was written to the tcri register before dma transfer start, the dmai is in initial state. (in the case a dma request occurs after writing to the dmae bit, the read value is a value written to the tcri register minus one.) if the read value is a value in the middle of transfer, the dmai is not in initial state. rej09b0392-0064 rev.0.64 oct 12, 2007 page 353 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.9 timers 24.9.1 timer a 24.9.1.1 timer a (timer mode) the timer is stopped after reset. set the mode, coun t source, counter value, and others using regis- ters taimr, tai, tacs0 to tacs2, and tapofs be fore setting the tais bit in the tabsr register to 1 (count starts) (i = 0 to 4). always make sure registers taimr, tacs0 to tacs2, and tapofs are modified while the tais bit is 0 (count stops) regardless of whether after reset or not. while counting is in progress, the counter value can be read out at any time by reading the tai regis- ter. however, if the counter is read at the same time it is reloaded, the value ffffh is read. also, if the counter is read before it starts counting after a value is set in the tai register while not counting, the set value is read. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register = 1 (three- phase output forcible cutoff by input on the sd pin enabled), pins ta1out, ta2out, and ta4out go to high-impedance state. rej09b0392-0064 rev.0.64 oct 12, 2007 page 354 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.9.1.2 timer a (eve nt counter mode) the timer is stopped after reset. set the mode, count source, counter value, and others using the taimr register, the tai register, the udf register, bits tazie, ta0tgl, and ta0tgh in the onsf register and the trgsr re gister, and tapos register before sett ing the tais bit in the tabsr regis- ter to 1 (count starts) (i = 0 to 4). always make sure the taimr register, the udf register, bits tazie, ta0tgl, and ta0tgh in the onsf register, the trgsr register, and tapofs regi ster are modified while the tais bit is 0 (count stops) regardless of whether after reset or not. while counting is in progress, the counter value can be read out at any time by reading the tai regis- ter. however, while reloading, ffffh can be read in underflow, and 0000h in overflow. when the counter is read before it starts counting after a value is set in the tai register while not counting, the set value is read. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register = 1 (three- phase output forcible cutoff by input on sd pin enabled), pins ta1out, ta2out, and ta4out go to high-impedance state. rej09b0392-0064 rev.0.64 oct 12, 2007 page 355 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.9.1.3 timer a (one-shot timer mode) the timer is stopped after reset. set the mode, count source, counter value, and others using the taimr register, the tai register, bits ta0tgl and ta0tgh in the onsf register, the trgsr regis- ter, registers tacs0 to tacs2 and the tapofs re gister before setting the tais bit in the tabsr register to 1 (count starts) (i = 0 to 4). always make sure the taimr register, bits ta0t gl and ta0tgh in the onsf register, the trgsr register, registers tacs0 to tacs2, and the tapofs register are modified while the tais bit is 0 (count stops) regardless of whether after reset or not. when setting the tais bit to 0 (count stops), the followings occur: ? a counter stops counting and a content of reload register is reloaded. ? the taiout pin outputs ?l? when the pofsi bit in the tapofs register is 0; outputs ?h? when 1. ? after one cycle of the cpu clock, the ir bit in th e taiic register is set to 1 (interrupt requested). output in one-shot timer mode synchronizes wi th a count source internally generated. when an external trigger is selected, one-and-half-cycle del ay of a count source as maximum occurs between a trigger input to the taiin pin and output in one-shot timer mode. the ir bit is set to 1 when timer operating mode is set with any of the following procedures: ? select one-shot timer mode after reset. ? change an operating mode from timer mode to one-shot timer mode. ? change an operating mode from event counter mode to one-shot timer mode. to use the timer ai interrupt (the ir bit), set the ir bit to 0 after the changes listed above are made. when a trigger occurs while counting, a counter reloads the reload register to continue counting after generating a re-trigger and counting down once. to generate a trigger while counting, generate a second trigger between generating the previous trigger and operating longer than one cycle of a timer count source. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register = 1 (three- phase output forcible cutoff by input on the sd pin enabled), pins ta1out, ta2out, and ta4out go to high-impedance state. rej09b0392-0064 rev.0.64 oct 12, 2007 page 356 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.9.1.4 timer a (pulse width modulation mode) the timer is stopped after reset. set the mode, count source, counter value, and others using the taimr register, the tai register, bits ta0tgl and ta0tgh in the onsf register, the trgsr regis- ter, registers tacs0 to tacs2, an d the tapof register be fore setting the tais bit in the tabsr reg- ister to 1 (count starts) (i = 0 to 4). always make sure the taimr register, bits ta0t gl and ta0tgh in the onsf register, the trgsr register, registers tacs0 to tacs2, and the tapofs register are modified while the tais bit is 0 (count stops) regardless of whether after reset or not. the ir bit is set to 1 when setting a timer oper ating mode with any of the following procedures: ? select pwm mode after reset. ? change an operating mode from timer mode to pwm mode. ? change an operating mode from event counter mode to pwm mode. to use the timer ai interrupt (ir bit), set the ir bi t to 0 by program after the changes listed above are made. when setting the tais register to 0 (count stop s) during pwm pulse output, the following action occurs. when the pofsi bit in the tapofs register is 0: ? stop counting. ? when the taiout pin is output ?h,? output le vel is set to ?l? and the ir bit is set to 1. ? when the taiout pin is output ?l,? both output level and the ir bit remains unchanged. when the pofsi bit in the tapofs register is 1: ? stop counting. ? when the taiout pin is output ?l,? output le vel is set to ?h? and the ir bit is set to 1. ? when the taiout pin is output ?h,? both output level and the ir bit remains unchanged. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register = 1 (three- phase output forcible cutoff by input on the sd pin enabled), pins ta1out, ta2out, and ta4out go to high-impedance state. rej09b0392-0064 rev.0.64 oct 12, 2007 page 357 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.9.2 timer b 24.9.2.1 timer b (timer mode) the timer is stopped after reset. set the mode, coun t source, counter value, and others using regis- ters tbimr, tbi, and tbcs0 to tb cs3 before setting the tbis bit in the tabsr or the tbsr register to 1 (count starts) (i = 0 to 5). always make sure the tbimr register and register s tbcs0 to tbcs3 are modified while the tbis bit is 0 (count stops) regardless of whether after reset or not. a value of a counter while counting, can be read in the tbi register at any time. ffffh is read while reloading. if the counter is read before it starts counting after a value is set in the tbi register while not counting, the set value is read. rej09b0392-0064 rev.0.64 oct 12, 2007 page 358 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.9.2.2 timer b (eve nt counter mode) the timer is stopped after reset. set the mode, count source, counter value, and others using the tbimr register and tbi register be fore setting the tbis bit in the tabsr or the tbsr register to 1 (count starts) (i = 0 to 5). always make sure the tbimr register is modified wh ile the tbis bit is 0 (count stops) regardless of whether after reset or not. while counting is in progress, the counter value can be read out at any time by reading the tbi regis- ter. however, if this register is read at the same time the counter is reloaded, the read value is always ffffh. if the tbi register is read after setting a va lue in it while not counting but before the counter starts counting, the read value is the value set in the register. rej09b0392-0064 rev.0.64 oct 12, 2007 page 359 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.9.2.3 timer b (pulse period / pulse width measurement mode) the timer is stopped after reset. set the mode, count source, etc. using t he tbimr register before setting the tbis bit in the t absr or the tbsr register to 1 (count starts) (i = 0 to 5). always make sure the tbimr register and register s tbcs0 to tbcs3 are modified while the tbis bit is 0 (count stops) regardless of whether after reset or not. to clear the mr3 bit to 0 by writing to the tbimr register while the tbis bit = 1 (count starts), be sure to write the same value as previously written to bits tmod0, tmod1, mr0, mr1, tck0, and tck1 and a 0 to bit 4. the ir bit in the tbiic register goes to 1 (interru pt requested) when an effective edge of a measure- ment pulse is input or timer bi is overflowed (i = 0 to 5). the factor of interrupt request can be deter- mined by use of the mr3 bit in the tbimr register within the interrupt routine. if the source of interrupt cannot be identified by the mr3 bit such as when the measurement pulse input and a timer overflow occur at the same time , use another timer to count the number of times timer b has overflowed. use the ir bit in the tbiic register to detect only overflows. use the mr3 bit only to determine the interrupt factor. when a count is started and the first effective edge is input, an indeterminate value is transferred to the reload register. at this time, time r bi interrupt request is not generated. a value of the counter is indeterminate after reset. if a count is started in this state, the mr3 bit may be set to 1 and timer bi interrupt request may be generated after a count start before an effective edge input. when a value is set to the tbi register while the tbis bit is 0 (count stops), the same value is written to the counter. for pulse width measurement, pulse widths are successively measured. use program to check whether the measurement result is ?h? level width or ?l? level width. rej09b0392-0064 rev.0.64 oct 12, 2007 page 360 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.10 serial interface 24.10.1 clock synchronous serial i/o 24.10.1.1 transmission / reception when the rts function is used with an external clock, rtsi pin (i = 0 to 2, 5 to 7) outputs ?l,? which informs the transmitting side that the mcu is ready for a receive operation. the rtsi pin outputs ?h? when a receive operation starts. therefore, a tran smit timing and receive ti ming can be synchronized by connecting the rtsi pin to the ctsi pin of the transmitting side. the rts function is disabled when an internal clock is selected. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register = 1 (three- phase output forcible cutoff by input on sd pin enabled), the following pins go to high-impedance state: p7_2/clk2/ta1out/v, p7_3/ cts2 / rts2 /ta1in/ v , p7_4/ta2out/w, p7_5/ta2in/ w , p8_0/ ta4out/rxd5/scl5/u, p8_1/ta4in/ cts5 / rts5 / u rej09b0392-0064 rev.0.64 oct 12, 2007 page 361 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.10.1.2 transmission if an external clock is selected, the following cond itions must be met while the external clock is held ?h? when the ckpol bit in the uic0 register (i = 0 to 2, 5 to 7) is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clo ck), or while the external clock is held ?l? when the ckpol bit is set to 1 (transmit da ta output at the rising edge and receive data input at the falling edge of the serial clock). ? the te bit in the uic1 register = 1 (transmission enabled) ? the ti bit in the uic1 register = 0 (data present in the uitb register) ?if cts function is selected, input on the ctsi pin = ?l? 24.10.1.3 reception in clock synchronous serial i/o mode, the shift clo ck is generated by activating a transmitter. set the uarti-associated registers for a transmit operation even if the mcu is used for receive operation only. dummy data is output from the txdi pin (i = 0 to 2, 5 to 7) while receiving. when an internal clock is selected , the shift clock is generated by setting the te bit in the uic1 regis- ter to 1 (transmission enabled) and placing dummy dat a in the uitb register. when an external clock is selected, set the te bit to 1 (transmission enabled) , place dummy data in the uitb register, and input an external clock to the clki pin to generate the shift clock. if data is received consecutively, an overrun error occurs when the ri bit in the uic1 register is set to 1 (data present in the uirb register) and the next receive data is received in the uarti receive regis- ter. and then, the oer bit in the uirb register is se t to 1 (overrun error occurred). at this time, the uirb register is undefined. if an overrun error occurs, the ir bit in the siric register remains unchanged. to receive data consecutively, set dummy data in the low-order byte in the uitb register per each receive operation. if an external clock is selected, the following cond itions must be met while the external clock is held ?h? when the ckpol bit is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock), or while the external clock is held ?l? when the ckpol bit is set to 1 (transmit data output at the risi ng edge and receive data input at the falling edge of the serial clock). ? the re bit in the uic1 register = 1 (reception enabled) ? the te bit in the uic1 register = 1 (transmission enabled) ? the ti bit in the uic1 register = 0 (data present in the uitb register) rej09b0392-0064 rev.0.64 oct 12, 2007 page 362 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.10.2 uart (clock asynch ronous serial i/o) mode 24.10.2.1 transmission / reception when the rts function is used with an external clock, rtsi pin (i = 0 to 2, 5 to 7) outputs ?l,? which informs the transmitting side that the mcu is ready for a receive operation. the rtsi pin outputs ?h? when a receive operation starts. therefore, a tran smit timing and receive ti ming can be synchronized by connecting the rtsi pin to the ctsi pin of the transmitting side. the rts function is disabled when an internal clock is selected. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register = 1 (three- phase output forcible cutoff by input on sd pin enabled), the following pins go to high-impedance state: p7_2/clk2/ta1out/v, p7_3/ cts2 / rts2 /ta1in/ v , p7_4/ta2out/w, p7_5/ta2in/ w , p8_0/ ta4out/rxd5/scl5/u, p8_1/ta4in/ cts5 / rts5 / u 24.10.2.2 transmission if an external clock is selected, the following cond itions must be met while the external clock is held ?h? when the ckpol bit in the uic0 register (i = 0 to 2, 5 to 7) is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clo ck), or while the external clock is held ?l? when the ckpol bit is set to 1 (transmit da ta output at the rising edge and receive data input at the falling edge of the serial clock). ? the te bit in the uic1 register = 1 (transmission enabled) ? the ti bit in the uic1 register = 0 (data present in the uitb register) ?if cts function is selected, input on the ctsi pin = ?l? 24.10.3 special mode 1 (i 2 c mode) when generating start, st op, and restart cond itions, set the stspsel bit in the uismr4 register (i = 0 to 2, 5 to 7) to 0 and wait for more than half cycl e of the transfer clock befo re setting each condition generation bit (stareq, rstareq, and stpreq) from 0 to 1. 24.10.4 special mode 4 (sim mode) a transmit interrupt request is generated by setting bits u2irs and u2ere in the u2c1 register to 1 (transmission completed) and 1 (e rror signal output), respectively . therefore, when using sim mode, make sure to clear the ir bit to 0 (interr upt not requested) after setting these bits. rej09b0392-0064 rev.0.64 oct 12, 2007 page 363 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.10.5 si/o3, si/o4 the souti default value which is se t to the souti pin by the smi7 bit approximately 10 ns may be out- put when changing the smi3 bit from 0 (i/o port) to 1 (souti output and clk function) while the smi2 bit in the sic to 0 (souti output) and the smi6 bit is set to 1 (internal clock). and then the souti pin is held high-impedance. if the output level from the souti pin is a problem when changing the smi3 bit from 0 to 1, set the default value of the souti pin by the smi7 bit. i = 3, 4 rej09b0392-0064 rev.0.64 oct 12, 2007 page 364 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.11 a/d converter set registers adcon0 (except bit 6), adcon1, and adcon2 when a/d conversion is stopped (before a trigger occurs). after a/d conversion is stopped, set the adstby bit from 1 to 0. when the adstby bit in the adcon1 register is cha nged from 0 (a/d operation stopped) to 1 (a/d oper- ation enabled), wait for 1 ad cycle or longer to start a/d conversion. to prevent noise-induced device malfunction or latchup, as well as to minimize conversion errors, insert capacitors between pins avcc, vref , analog input (ani (i = 0 to 7) , an0_i, an2_i), and avss. similarly, insert a capacitor between pins vcc1 and vss. fi gure 24.4 shows an example connection of individual pin. make sure the port direction bits corresponding to the pins that are used as analog inputs are set to 0 (input mode). when the trg bit in the adcon0 register = 1 (external trigger), make sure the port direction bit for the adtrg pin is set to 0 (input mode). when using key input interrupts, do not use any of the fo ur pins an4 to an7 as analog inputs. (a key input interrupt request is generated when the a/d input voltage goes low.) when changing an a/d operating mode, set bits ch2 to ch0 in the adcon0 register and bits scan1 to scan0 in the adcon1 register again to select analog input pins. figure 24.4 use of capacitors to reduce noise vcc1 vss avcc avss vref ani c4 c1 c2 c3 microcomputer notes : 1. c1 0.47mf, c2 0.47mf, c3 100pf, c4 0.1mf, c5 0.1mf (reference) 2. use thick and shortest possible wiring to connect capacitors. vcc2 vss c5 vcc1 vcc1 vcc2 ani: ani, an0_i, and an2_i (i = 0 to 7) vcc1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 365 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions when a/d conversion is forcibly terminated by sett ing the adst bit in the ad0con0 register to 0 (a/d conversion stops) by program during a/d conversion , the a/d conversion result is undefined. the adi register not performing a/d conversion may also be undef ined. if the adst bit is set to 0 by program dur- ing a/d conversion, do not use values obtained from any adi registers. the applied intermediate potential may cause more increase in power consumption to an4 to an7 than to other analog input pins (an0 to an3, an0_0 to an 0_7, and an2_0 to an2_7) since an4 to an7 are used with ki0 to ki3. when a/d conversion is stopped in one-shot mode or single sweep mode, the adst bit in the adcon0 register becomes 0 (a/d conversion stop). also, when a trigger by adtrg is selected, the adst bit becomes 0. therefore, set the adst bit to 1 (a/d conv ersion start) by a program if there is a possibility that a trigger is input subsequently. connect the vref pin to vcc1 pin. because the vr ef pin is connected to vcc1 pin inside, current flows if potential difference occurs between the pins. rej09b0392-0064 rev.0.64 oct 12, 2007 page 366 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.12 programmable i/o ports if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register = 1 (three-phase output forcible cutoff by input on the sd pin enabled), pins p7_2 to p7_5 and p8_0 and p8_1 go to high- impedance state. setting the sm32 bit in the s3c register to 1 causes the p9_2 pin to go to high-impedance state. similarly, setting the sm42 bit in the s4c register to 1 causes the p9_6 pin to go to high-impedance state. rej09b0392-0064 rev.0.64 oct 12, 2007 page 367 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.13 flash memory version 24.13.1 functions to inhibi t rewriting flash memory id codes are stored in addresses 0fffdfh, 0fffe3h, 0fffebh, 0fffefh, 0ffff3h, 0ffff7h, and 0ffffbh. if wrong data are written to theses address es, the flash memory cannot be read or written in standard serial i/o mode. the romcp register is mapped in address 0fffffh. if wrong data is written to this address, the flash memory cannot be read or written in parallel i/o mode. in the flash memory version of microcomputer, t hese addresses are allocated to the vector addresses (h) of fixed vectors. 24.13.2 stop mode when the microcomputer enters stop mode, execute the instruction which sets the cm10 bit in the cm1 register to 1 (stop mode) after setting the fmr01 bit in the fmr0 register to 0 (cpu rewrite mode dis- abled) and disabling the dma transfer. 24.13.3 wait mode when shifting to wait mode, set the fmr01 bit to 0 (cpu rewrite mode disabled) before executing the wait instruction. 24.13.4 low power consumption mode, on -chip oscillator low power consump- tion mode if the cm05 bit in the cm0 register is set to 1 (main clock stop), do not execute the following com- mands. ?program ? block erase ? lock bit program 24.13.5 writing command and data write the command code and data at even addresses. 24.13.6 program command write xx41h in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data prog ram and verify) will start. make su re the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle. 24.13.7 lock bit program command write xx77h in the first bus cycle and write xxd0h in the second bus cycle to the highest-order even address of a block, and the lock bit for the specified bl ock is cleared to 0. make sure then address value specified in the first bus cycle is the same highest-order block address that is specified in the second bus cycle. rej09b0392-0064 rev.0.64 oct 12, 2007 page 368 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.13.8 operation speed before entering cpu rewrite mode (ew0 or ew1 mode), set the cm11 bit in the cm1 register to 0 (main clock), select 10 mhz or less for cpu cloc k using the cm06 bit in the cm0 register and bits cm17 and cm16 in the cm1 register. also, set the pm17 bit in the pm1 register to 1 (with wait state). 24.13.9 instructions inhibited against use the following instructions cannot be used in ew0 mode because the flash memory internal data is referred: und instruction, into in struction, jmps instruction, jsrs instruction, and brk instruction. 24.13.10 interrupts ew0 mode ? any interrupt which has a vector in the relocatable vector table can be used providing that its vector is transferred into the ram area. ? the nmi and watchdog timer (oscillation stop, re-oscillation detect, and low vo ltage detect) inter- rupts can be used because registers fmr0 and fmr1 are initialized when one of those interrupts occurs. the jump addresses for those interrupt routines should be set in the fixed vector table. ? because the rewrite operation stops when an nmi or watchdog timer (oscilla tion stop, re-oscillation detect, and low voltage detect) interrupt occurs, the rewrite program must be executed again after exiting the interrupt routine. ? the address match interrupt cannot be used because the flash memory internal data is referred. ew1 mode ? make sure that any interrupt which has a vector in the relocatable vector table or address match interrupt will not be accept ed during the auto progra m or auto erase period. ? avoid using watchdog timer (osc illation stop, re-oscilla tion detect, and low vo ltage dete ct) inter- rupts. ? the nmi interrupt can be used because registers fmr0 and fmr1 are initializ ed when this inter- rupt occurs. the jump address for the interrupt ro utine should be set in the fixed vector table. ? because the rewrite operation is halted when an nmi interrupt occurs, execute the rewrite program again after exiting the interrupt routine. 24.13.11 how to access to set the fmr01, fmr02, or fmr11 bit to 1, write 0 and then 1 in succession. ensure that no inter- rupts or dma transfers will o ccur before writing 1 after writ ing 0. perform it when the nmi pin is ?h? level if the pm24 bit is 1 ( nmi ). 24.13.12 writing in the user rom area ew0 mode ? if the power supply voltage drops while rewriting any block in which the rewrite control program is stored, the rewrite control program may not be co rrectly rewritten and, consequently, the flash memory becomes unable to be rewritten thereafter. in this case, use standard serial i/o or parallel i/o mode. ew1 mode ? avoid rewriting any block in which t he rewrite control program is stored. 24.13.13 dma transfer in ew1 mode, make sure that no dm a transfers will occur while the fm r00 bit in the fmr0 register = 0 (during the auto program or auto erase period). rej09b0392-0064 rev.0.64 oct 12, 2007 page 369 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.13.14 programming / erasing endurance and execution time as the number of programming / erasing times increases, so does the execution time for software com- mands (program, block erase, and lock bit program commands). the software commands are stopped by hardware reset 1, brown-out reset, nmi interrupt, and watch- dog timer (oscillation stop , re-oscillation detect, and low voltage detect) interrupt. if a software com- mand is stopped by such reset or interrupt, erase the block in process befo re reexecuting the stopped command. rej09b0392-0064 rev.0.64 oct 12, 2007 page 370 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group 24. precautions 24.14 noise connect a bypass capacitor (approximately 0.1 f) across pins vcc1 and vss, and pins vcc2 and vss using the shortest and thicker possible wiring. fi gure 24.5 shows the bypass capacitor connection. figure 24.5 bypass capacitor connection bypass capacitor connecting pattern connecting pattern bypass capacitor connecting pattern connecting pattern m16c / 64 group vss vss vcc2 vcc1 rej09b0392-0064 rev.0.64 oct 12, 2007 page 371 of 373 under development preliminary specification specification in this preliminar y version is subject to change. m16c/64 group appendix 1. package dimensions appendix 1.package dimensions p-qfp 100 - 1 4 x20 - 0 . 65 1 .8 g mass [ty p .] 100 p 6 f- a p r qp 0100 j d - b r ene sas c o d e jeit a packa g e c o d e pre v io u s c o d e 0 . 2 0 . 15 0 . 13 0 .4 0 . 3 0 . 25 m a x nom m in d imension in m illime t ers s ym b ol r e f erence 20 . 2 20 . 0 1 9.8 d 1 4. 2 1 4. 0 13 .8 e 2 .8 a 2 23 . 1 22 .8 22 . 5 17 . 1 16 .8 16 . 5 3 . 05 a 0 . 2 0 . 1 0 0 .8 0 . 6 0 .4 l 10 0 c 0 . 65 e 0 . 10 y h d h e a 1 b p z d z e 0 . 575 0 .8 25 x 0 . 13 2 . 1 . d i m en s i o n s " * 1 " a n d " * 2 " do n o t in c l ud e mo l d fl as h. n o te ) d i m en s i o n " * 3 " do e s n o t in c l ud e t r i m o ff s et. d e t ail f l a 2 a 1 * 3 * 1 * 2 f 1 30 31 50 51 8 0 8 1 100 in d e x mark y x c h e e d h d a b p z d z e e u n d er d e v elo p men t terminal cross sec t ion b 1 c 1 b p c 2 . 1 . d i m en s i o n s " * 1 " a n d " * 2 " do n o t in c l ud e mo l d fl as h. n o te ) d i m en s i o n " * 3 " do e s n o t in c l ud e t r i m o ff s et. y in d e x mark x 125 26 50 51 75 76 100 f * 1 * 3 * 2 z e z d e d h d h e b p d e t ail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0 . 0 8 e 0 . 5 c 0 8 x l 0 . 35 0 . 5 0 . 65 0 . 05 0 . 1 0 . 15 a 1 . 7 15 .8 16 . 016 . 2 15 .8 16 . 016 . 2 a 2 1 .4 e 13 .9 1 4. 01 4. 1 d 13 .9 1 4. 01 4. 1 r e f erence s ym b ol d imension in m illime t ers m in nom m a x 0 . 15 0 . 20 0 . 25 0 . 0 9 0 . 1 4 5 0 . 20 0 . 0 8 1 . 0 1 . 0 0 . 1 8 0 . 125 1 . 0 pre v io u s c o d e jeit a packa g e c o d e r ene sas c o d e plqp 0100 k b - a 100 p 6 q- a / fp- 100u / fp- 100u v mass [ty p .] 0 . 6g p-lqfp 100 - 1 4 x1 4- 0 . 50 e rej09b0392-0064 rev.0.64 oct 12, 2007 page 372 of 373 m16c/64 group register index under development preliminary specification specification in this preliminar y version is subject to change. register index a ad0 to ad7 ............................................ 233 adcon0, adcon1 ...................................... ........................ 232, 235, 237, 239, 241, 243 adcon2 ................................................ 233 adic .............................................. 105, 106 aier ....................................................... 117 aier2 ..................................................... 117 b bcnic ............................................ 105, 106 c cm0 ......................................................... 76 cm1 ......................................................... 77 cm2 ......................................................... 78 cpsrf ........................................... 141, 156 crcd ..................................................... 248 crcin .................................................... 248 cse .......................................................... 62 cspr ..................................................... 120 csr ......................................................... 55 d d4int ....................................................... 39 da0, da1 ............................................... 247 dacon .................................................. 247 dar0 to dar3 ....................................... 128 dbr ......................................................... 67 dm0con to dm3con ........................... 127 dm0ic .................................................... 106 dm0ic to dm3ic .................................... 105 dm0sl to dm3sl .................................. 125 dtt ........................................................ 169 f fmr0 ..................................................... 272 fmr1 ..................................................... 273 fmr6 ..................................................... 275 i ictb2 ..................................................... 169 idb0, idb1 ............................................. 169 ifsr ....................................................... 113 ifsr2a, ifsr3a .................................... 114 int0ic to int7ic ................................... 106 invc0 ..................................................... 167 invc1 ..................................................... 168 k kupic .................................................... 105 o ofs1 .............................................. 120, 269 onsf ..................................................... 140 p p0 to p10 ............................................... 257 pclkr ..................................................... 79 pcr ................................................ 114, 259 pd0 to pd10 .......................................... 256 plc0 ........................................................ 80 pm0 .......................................................... 48 pm1 .......................................................... 49 pm2 .......................................................... 79 prcr ....................................................... 98 prg2c ..................................................... 50 pur0, pur1 .......................................... 258 pur2 ...................................................... 259 r rmad0 to rmad3 ................................. 117 rstfr ..................................................... 46 s s0ric to s2ric, s5ric to s7ric ......... 105 s0tic to s2tic, s5tic to s7tic .......... 105 s34c2 .................................................... 225 s3brg, s4brg ..................................... 224 s3c, s4c ............................................... 224 s3ic, s4ic ............................................. 106 s3trr, s4trr ...................................... 224 sar0 to sar3 ....................................... 128 rej09b0392-0064 rev.0.64 oct 12, 2007 page 373 of 373 m16c/64 group register index under development preliminary specification specification in this preliminar y version is subject to change. t ta0 to ta4 ............................................. 138 ta0ic to ta4ic ...................................... 105 ta0mr to ta4mr .. 138, 143, 145, 150, 152 ta1, ta2 ................................................ 170 ta11 ....................................................... 170 ta1mr, ta2mr ..................................... 172 ta21 ....................................................... 170 ta2mr to ta4mr .................................. 147 ta4 ......................................................... 170 ta41 ....................................................... 170 ta4mr ................................................... 172 tabsr ................................... 139, 156, 171 tacs0, tacs1 ...................................... 141 tacs2 .................................................... 142 tapofs ................................................. 142 tb0 to tb5 ............................................. 155 tb0ic to tb5ic ...................................... 105 tb0mr to tb5mr .......... 155, 159, 161, 163 tb2 ........................................................ 171 tb2mr ................................................... 172 tb2sc ................................................... 170 tbcs0 to tbcs3 ................................... 157 tbsr ..................................................... 156 tcr0 to tcr3 ....................................... 128 trgsr .......................................... 140, 171 u u0bcnic, u1bcnic, u5bcnic to u7bcnic ................................................................ 105 u0brg to u2brg ................................. 180 u0c0 to u2c0 ........................................ 181 u0c1 to u2c1 ........................................ 182 u0mr to u2mr ...................................... 180 u0rb to u2rb ....................................... 179 u0smr to u2smr ................................. 183 u0smr2 to u2smr2 ... .......................... 184 u0smr3 to u2smr3 ... .......................... 184 u0smr4 to u2smr4 ... .......................... 185 u0tb to u2tb ........................................ 179 u1bcnic ............................................... 106 u5bcnic?`u7bcnic ............................ 106 u5brg to u7brg ................................. 180 u5c0 to u7c0 ........................................ 181 u5c1 to u7c1 ........................................ 182 u5mr to u7mr ...................................... 180 u5rb to u7rb ....................................... 179 u5smr to u7smr ................................. 183 u5smr2 to u7smr2 ... .......................... 184 u5smr3 to u7smr3 ... .......................... 184 u5smr4 to u7smr4 ... .......................... 185 u5tb to u7tb ........................................ 179 ucon ..................................................... 183 udf ........................................................ 139 v vcr1 ........................................................ 38 vcr2 ........................................................ 38 vw0c ....................................................... 40 w wdts ..................................................... 119 a- 1 revision history m16c/64 group hardware manual rev. date description page summary 0.51 jun 06, 2007 - first edition issued. 0.61 jun 22, 2007 3 table 1.2 specific ations (2) is partly revised. 4 table 1.3 product list is partly revised. 0.62 jul 04, 2007 17 3. memory (including the figure) is partly revised. 32 figure 5.1 example reset circuit is partly revised. 51 7.3 internal memory is partly revised. 75 figure 10.1 system clock generation circuit is partly revised. 163 figure 15.24 tbimr register in pulse period and pulse width measurement mode is partly revised. 186 table 17.1 clock synchronous serial i/o mode specifications is partly revised. 220 figure 17.33 transmit and receive timing in sim mode is partly revised. 224 figure 17.38 registers s3c, s4c, s3brg, s4brg, s3trr, and s4trr is partly revised. 256 table 19.2 one-shot mode specifications is partly revised. 260 table 19.4 single sweep mode specifications is partly revised. 267 figure 19.9 analog input pin and external sensor equivalent circuit is 264 22.1 memory map is partly revised. 287 23.1.1 boot mode is partly revised. 265 22.1.2 user boot function is added. 290 23.2.4 standard serial i/o mode disable function is added. 267 22.2.2 id code check function is added. 268 22.2.3 forced erase function is added. 319 figure 23.20 pin connections for stand ard serial i/o mode (1) is partly revised. 320 figure 23.21 pin connections for stand ard serial i/o mode (2) is partly revised. 321 figure 23.22 circuit application in standard serial i/o mode 1 is partly revised. 322 figure 23.23 circuit application in standard serial i/o mode 2 is partly revised. 343 24.5 power control is partly revised. 362 24.11 a/d converter is partly revised. 0.63 sep 21, 2007 3 table 1.2 specif ications (2) is partly revised. 5 figure 1.2 marking diagram of flas h memory version (top view) is partly revised. 29 table 4.12 sfr information (12) is partly revised. 79 figure 10.5 pm2 register is partly revised. 92 table 10.7 pin status in stop mode is partly revised. 114 figure 12.12 registers ifsr2a, if sr3a, and pcr is partly revised. 234 table 18.2 one-shot mode specifications is partly revised. 238 table 18.4 single sweep mode specifications is partly revised. 259 figure 21.11 pcr register is partly revised. 263 table 22.1 flash memory version specifications is partly revised. a- 2 263 table 22.2 flash memory rewrite modes overview is partly revised. 268 22.1.3 standard serial i/o mode disable function is moved to 22.2.4. 268 table 22.8 forced erase function is partly revised 272 figure 22.5 fmr0 register is partly revised. 274 figure 22.7 fmr2 register is partly revised. 303 figure 23.3 a/d conversion characteristics is partly revised. 304 table 23.5 flash memory version el ectrical characteristics is partly revised. 0.64 oct 12, 2007 3 table 1.2 specif ications (2) is partly revised. 11 table 1.6 pin functions (1) is partly revised. 13 table 1.8 pin functions (3) is parly revised. 32 figure 5.1 example reset circuit is partly revised. 92 10.4.3 stop mode is partly revised. 230 table 18.1 a/d converter specifications is partly revised. 231 figure 18.1 a/d converter block diagram is partly revised. 233 figure 18.3 registers adcon2 and ad0 to ad7 is partly revised. 234 table 18.2 one-shot mode specifications is partly revised. 235 figure 18.4 registers adcon0 and adcon1 (one-shot mode) is partly revised. 236 table 18.3 repeat mode spec ifications is partly revised. 237 figure 18.5 registers adcon0 and adcon1 (repeat mode) is partly revised. 238 table 18.4 single sweep mode specifications is partly revised. 239 figure 18.6 registers adcon0 and adcon1 (single sweep mode) is partly revised. 240 table 18.5 repeat sweep mode 0 specifications is partly revised. 241 figure 18.7 registers adcon0 and adcon1 (repeat sweep mode 0) is partly revised. 242 table 18.6 repeat sweep mode 1 specifications is partly revised. 243 figure 18.8 registers adcon0 and adcon1 (repeat sweep mode 1) is partly revised. 260 table 21.1 unassigned pin handling in single-chip mode is partly revised. 261 table 21.2 unassigned pin handling in memory expansion mode and microprocessor mode is partly revised. 262 figure 21.12 unassigned pin handling is partly revised. 295 table 22.13 pin functions (flash memory standard serial i/o mode) is partly revised. 301 table 23.1 absolute maximu m ratings is partly revised. 302 table 23.2 recommended operatin g conditions is partly revised. 303 table 23.3 a/d conversion characteristics is partly revised. 307 table 23.9 electrical characteristics (1) is partly revised. 342 24.2.1 vcc1 is added. 342 24.2.2 cnvss is added. 364 figure 24.4 use of capacitors to reduce noise is partly revised. 365 24.11 a/d converter is partly revised. revision history m16c/64 group hardware manual rev. date description page summary m16c/64 group hardware manual publication date: feb 28, 2007 rev.0.20 oct 12, 2007 rev.0.64 published by: sales strategic planning div. renesas technology corp. 2-6-2, otemachi, chiyoda-ku, tokyo 100-0004 ? 2007. renesas technology corp., all rights reserved. printed in japan. m16c/64 group hardware manual 2 - 6 - 2 , ot e-mac h i, ch iyo d a-k u , tokyo, 100 - 000 4, ja p an |
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